Memory repair circuit and method
AssigneeLogicVision, Inc.
InventorsBenoit Nadeau-Dostie, Saman M. I. Adham
Life of this patent
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Abstract
A self-repair circuit for a semiconductor memory provides input and output test selectors coupled to respective data bit group inputs and outputs, respectively and input and output repair selectors coupled between the input and output test selectors and functional inputs and functional outputs, respectively. This arrangement allows all data bit groups to be tested in one pass and all test and repair selector circuitry to be tested.
Claims18
A method of repairing a semiconductor memory having a number of data bit groups greater than that required to store functional data words so as to provide one or more redundant data bit groups for repairing said memory, each data bit group having a data input and a data output, and non-redundant data bit groups having a default functional input and a default functional output, said method comprising:
- prior to performing a memory test, inserting into a circuit containing said memory, an input test selector connected to the data bit input of each data bit group and an output test selector connected to the data bit output of each data bit group and inserting input repair selectors between functional inputs and said input test selectors and output repair selectors between said output test selectors and functional outputs;
- performing a memory test of all data bit groups in said memory to identify all data bit groups having at least one defective data bit;
- storing a test result for each data bit group;
- and
- selecting a functional input for each data bit group and a data bit group for each functional output based on said test result and a functional input and output index (I/O index).
A self-repair circuit for a semiconductor memory having a number of data bit groups greater than that required to store functional data words to provide redundant data bit groups for repairing said memory, each data bit group having a data input and a data output, and non-redundant data bit groups having a default functional input and a default functional output, said circuit comprising:
- input and output test selectors coupled to respective data bit group inputs and outputs, respectively;
- input and output repair selectors coupled between said input and output test selectors and functional inputs and functional outputs, respectively;
- said input test selectors being responsive to a memory test control signal, and each having an output coupled to an associated data bit group input and to outputs of associated input repair selectors;
- said output test selectors being responsive to a scan test control signal, and being coupled to associated data bit group output and to associated output repair selectors;
- said input repair selectors selectively connecting each functional input to a default data bit group input and to a number of adjacent data bit group inputs equal to the number of redundant data bit groups via said input test selectors;
- said output repair selectors selectively connecting each functional output to a default data bit group output and to said number of adjacent data bit group outputs via said output test selectors.
Dependencies are inferred from the claim text.