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US 7,257,727 B2Granted
Timer systems and methods
AssigneeLattice Semiconductor Corporation
InventorEdward A. Ramsden
Life of this patent
Estimating the term…
Abstract
Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells each having a multiplexer and a counter.
Claims20
A timer comprising:
- a prescaler adapted to receive an input clock signal and provide a plurality of different output clock signals;
- and
- a timer cell comprising:
- a first multiplexer adapted to select from the output clock signals from the prescaler and the input clock signal to provide a counter clock signal;
- and
- a counter adapted to receive the counter clock signal, a reset signal, and a preloadable control signal and provide a timer output signal;
- and
- wherein the counter is a preloadable counter with an enable terminal and a parallel load terminal, and wherein the timer output signal is fed back to the enable terminal, with the parallel load terminal receiving the reset signal.
5 more elements
A programmable logic device comprising:
- a prescaler adapted to receive an input clock signal and provide a number of output clock signals;
- a first multiplexer adapted to select from at least the output clock signals from the prescaler based on a first control signal and provide a counter clock signal;
- and
- a counter adapted to receive the counter clock signal and a preloadable control signal and provide a timer output signal, wherein the timer output signal is fed back as an enable signal for the counter.
1 more element
A method of providing a timer signal, the method comprising:
- receiving an input clock signal;
- generating a number of different clock signals based on the input clock signal;
- selecting one clock signal from among the different clock signals to provide as a counter clock signal;
- providing a counter adapted to receive the counter clock signal and a control signal, which controls a timer period for the counter, and to provide a timer output signal;
- and
- providing the timer output signal to an enable terminal of the counter, wherein the counter is further adapted to receive a reset signal, which controls the loading of bits into the counter from the control signal.
3 more elements
Dependencies are inferred from the claim text.