Circuit for generating wait signal in semiconductor device
AssigneeHynix Semiconductor Inc.
InventorDuk Ju Jeong
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Abstract
The present invention discloses a circuit for generating a wait signal in a semiconductor device. Even if an address input enable signal is synchronized with a clock and continuously or irregularly inputted, the circuit for generating the wait signal in the semiconductor device generates the wait signal suitable for a latency counter by using the finally-inputted address input enable signal. In addition, the circuit for generating the wait signal in the semiconductor device generates the wait signals having various pulse widths to be suitable for various latency counters, and enables the object wait signal earlier than data input or output by one clock, or simultaneously with data input or output.
Claims15
A circuit for generating a wait signal in a semiconductor device, comprising:
- a latch unit for sequentially generating a plurality of latch signals by shifting an address input enable signal in every clock;
- a wait signal generating unit for generating a plurality of wait signals corresponding to latency counter values according to the plurality of latch signals;
- a wait signal selecting and transmitting unit for outputting the wait signal corresponding to the target latency counter value among the plurality of wait signals according to a plurality of latency counter signals and a wait output control signal;
- and
- an output unit for determining a logic state of the wait signal and outputting the wait signal according to an output state control signal and a chip select signal.
Dependencies are inferred from the claim text.