US 7,257,725 B2Granted

Memory system

AssigneeElpida Memory, Inc.

InventorsHideki Osaka, Toyohiko Komatsu, Masashi Horiguchi, Susumu Hatano, Kazuya Ito

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Abstract

A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.

Claims7

Dependent claims

A memory system comprising:

a memory controller;
a clock generator, connected to said memory controller through a first clock signal line, for propagating a clock signal along said first clock signal line toward said memory controller;
a plurality of second clock signal lines extended to be parallel and adjacent respectively to said first clock signal line, one end of said plurality of second clock signal lines being connected to terminating resistance respectively so that, when the clock signal is propagated along said first clock signal line, a crosstalk signal is propagated along said plurality of second clock signal lines in a direction opposite to the propagation direction of said clock signal;
a plurality of memory modules connected to the other ends of said plurality of second clock signal lines;
a data wired line which is provided for each of said plurality of memory modules and on which a data signal is transmitted between the corresponding memory module to which said data wired line is connected and said memory controller, said data wired line having substantially the same length as that of a portion of said first and second clock signal lines formed between said corresponding memory module and said memory controller;
and
a signal line which is provided for each of said plurality of memory modules and by which said corresponding memory module is connected to said memory controller, said signal line having substantially the same length as that of said data wired line;
wherein said memory controller comprises
(i) a location detection circuit which transmits, prior to performing write access to said plurality of memory modules, a location detection signal to the memory module to which write access is performed through said signal line and receives a reflected signal from said memory module, thereby measuring a physical quantity corresponding to a signal propagation time between said memory module and said memory controller;
and
(ii) an adjustment circuit which controls timing, at which the data signal is transmitted from said memory controller to said memory module through said data wired line, according to the physical quantity so as to eliminate a phase difference in propagation delay times caused by the length of said data wired line.

8 more elements

A memory system comprising:

a memory controller;
a clock generator, connected to said memory controller, for propagating a clock signal on a clock signal line between said memory controller and said clock generator,
one ends of said plurality of signal lines being connected to terminating resistances respectively so that. when the clock signal is propagated along said clock signal line, a crosstalk signal is propagated along said signal line in a direction opposite to the propagation direction of said clock signal;
and
a plurality of memory modules connected to the other ends of said plurality of signal lines;
wherein said memory controller comprises
(i) a transmission circuit for transmitting, prior to write access to one of the memory modules, a location detection signal to said memory module, a reflected-signal detection circuit connected at its input to an output of said transmission circuit for measuring a physical quantity corresponding to a signal propagation time between said memory module and memory controller;
and
(ii) an adjustment circuit for controlling timing of transmission of the write data according to said physical quantity so as to eliminate a phase difference in propagation delay times caused by the length of the wired line to said memory module for write access to said memory module;
and
wherein said adjustment circuit controls the timing of transmission of the write data according to values obtained by calculating said physical quantity, propagation delay time corresponding to a distance between an input of a memory device in said memory module and a connection point between said memory module and said data wired line, and a required signal time between clock and data terminals prescribed by specifications of said memory device.

8 more elements

Dependencies are inferred from the claim text.