Reducing power consumption in embedded systems by controlling voltage based on system state and partition designation

A method of performing time optimization for an embedded system, the method comprising:

• selecting multiple, critical paths in the embedded system;
• generating a timing margin vector for each critical path using a time delay circuit, wherein each bit of the timing margin vector corresponds to a stage of the time delay circuit;
• and
• determining a worst-case timing margin vector based on the timing margin vectors,
• wherein generating the timing margin vector includes:
• comparing an output signal from a critical path to propagated signals corresponding to stages of the time delay circuit;
• providing a first logic value to the timing margin vector if the output signal and the propagated signal are identical logic values;
• and
• providing a second logic value to the timing margin vector if the output signal and the propagated signal are not identical logic values;
• and
• wherein determining the worst-case timing margin vector includes:
• comparing the bits associated with a same stage of the plurality of time delay circuits;
• providing the first logic value to the worst-case timing margin vector if the bits are identical logic values;
• and
• providing the second logic value to the worst-case timing margin vector if the bits are not identical logic values.

A timing feedback module for generating a timing margin vector, the timing feedback module including:

• a time delay circuit coupled to receive an output of a critical path in an integrated circuit;
• and
• a compare circuit for comparing the output signal of the critical path to propagated signals associated with stages on the time delay circuit,
• wherein the compare circuit includes:
• a plurality of XOR gates, each XOR gate for receiving the output signal of the critical path and one of the propagated signals;
• a first plurality of OR gates, each OR gate for receiving an output of the XOR gate;
• and
• a plurality of flip-flops, each flip-flop for receiving an output of the OR gate and providing an output to another input terminal of the OR gate, the output forming a predetermined bit of a timing margin vector.