Bootable NAND flash memory architecture

A bootable NAND flash memory comprising:

• a plurality of instruction storage locations;
• a plurality data lines adapted for outputting instructions stored in the plurality of data storage locations;
• an internal address register adapted for storing address information associated with a memory location in which is stored one of a plurality instructions associated with a boot sequence is to be output on the data lines;
• means for switching to a sequential mode in accordance with a boot signal representative of a commencement of a boot code sequence;
• means for loading a preselected address into the internal address register responsive to the means for switching to a sequential mode;
• counter means for sequentially incrementing the internal address register so that instructions of the boot sequence sequentially appear on the data lines until completion thereof so as to be synchronous with an instruction fetch sequence of an associated processor;
• and
• means for switching to a normal operating mode upon de-assertion of the boot signal.

A method of running programs disposed in a non-externally addressable memory comprising the steps of:

• receiving a run signal representative of a commencement of a preselected code sequence disposed in the non-externally addressable memory;
• upon receipt of the run signal, switching to a sequential mode of operation and preloading an internal address register with a preselected address corresponding with a first instruction of the code sequence;
• outputting an instruction associated with the address of the internal address register;
• incrementing the internal address register so as to output each instruction forming the preselected code sequence synchronously with an instruction fetch sequence of an associated processor;
• and
• switching to a normal mode of operation after each instruction forming the preselected code sequence has been output.

An externally non-addressable memory for outputting an executable code sequence comprising:

• a plurality of data storage locations;
• a plurality data lines adapted for outputting data stored in the plurality of data storage locations;
• an internal address register storing address information associated with a memory location associated with an instruction to be output on the data lines, the internal address register receiving a preselected address upon receipt of a run signal representative of a commencement of a preselected code sequence comprised of a plurality of executable instructions stored in the plurality of data storage locations signal;
• a counter to sequentially increment a content of the internal address register in response to a clock signal so that instructions of the code sequence sequentially appear on the data lines in series responsive to the run instruction synchronously with an instruction fetch sequence of an associated processor;
• and
• means for switching to a normal mode of operation after the code sequence has been output.