Avoiding register RAW hazards when returning from speculative execution

An apparatus that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode, comprising:

• a processor with an in-order architecture;
• a short-latency scoreboard within the processor, which delays issuance of instructions that depend upon uncompleted short-latency instructions;
• and
• an execution mechanism configured to issue instructions for execution in program order during execution of a program in a normal-execution mode;
• wherein upon encountering a condition (a launch condition) during an instruction (a launch-point instruction) that causes the processor to enter the speculative-execution mode, the execution mechanism is configured to,
• generate a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and to
• commence execution in the speculative-execution mode;
• wherein upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the execution mechanism is configured to use the checkpoint to resume execution in the normal-execution mode from the launch-point instruction;
• and
• wherein while resuming execution in the normal-execution mode, the execution mechanism is configured to ensure that entries that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for when resuming execution from the launch-point instruction;
• and
• wherein while generating the checkpoint, the execution mechanism is configured tosave a precise architectural state of the processor to facilitate subsequent recovery from exceptions that arise during the speculative-execution mode.

A computer system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode, comprising:

• a processor with an in-order architecture;
• a memory;
• a short-latency scoreboard within the processor, which delays issuance of instructions that depend upon uncompleted short-latency instructions;
• and
• an execution mechanism within the processor configured to issue instructions for execution in program order during execution of a program in a normal-execution mode;
• wherein upon encountering a condition (a launch condition) during an instruction (a launch-point instruction) that causes the processor to enter the speculative-execution mode, the execution mechanism is configured to,
• generate a checkpoint that can subsequently be used to return execution of the program to the launch-point instruction, and to
• commence execution in the speculative-execution mode;
• wherein upon encountering a condition that causes the processor to leave the speculative-execution mode and return to the launch-point instruction, the execution mechanism is configured to use the checkpoint to resume execution in the normal-execution mode from the launch-point instruction;
• and
• wherein while resuming execution in the normal-execution mode, the execution mechanism is configured to ensure that entries that were in the short-latency scoreboard prior to entering the speculative-execution mode, and which are not yet resolved, are accounted for when resuming execution from the launch-point instruction;
• and
• wherein while generating the checkpoint, the execution mechanism is configured tosave a precise architectural state of the processor to facilitate subsequent recovery from exceptions that arise during the speculative-execution mode.