Selective execution of deferred instructions in a processor that supports speculative execution

An apparatus for selectively executing deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution, comprising:

• a processor;
• an execution mechanism within the processor that is configured to issue instructions for execution in program order during a normal-execution mode;
• wherein when a long-latency operation is encountered, the execution mechanism is configured to record the long-latency operation in a long-latency scoreboard wherein each position in the long-latency scoreboard includes a deferred buffer start index;
• wherein upon encountering an unresolved data dependency during execution of an instruction, the execution mechanism is configured to perform a checkpointing operation and execute subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred into a deferred buffer, and wherein other non-deferred instructions are executed in program order,
• wherein upon encountering a deferred instruction that depends on a long-latency operation within the long-latency scoreboard, the execution mechanism is configured to update the deferred buffer start index associated with the long-latency operation to point to position in the deferred buffer occupied by the deferred instruction;
• and
• wherein when a long-latency operation returns, the execution mechanism is configured to execute all of the instructions in the deferred buffer starting at the deferred buffer start index for the returning long-latency operation.

A computer system for selectively executing deferred instructions following a return of a long-latency operation in a processor that supports speculative-execution, comprising:

• a memory;
• a processor;
• an execution mechanism within the processor which is configured to issue instructions for execution in program order during a normal-execution mode;
• wherein when a long-latency operation is encountered, the execution mechanism is configured to record the long-latency operation in a long-latency scoreboard wherein each position in the long-latency scoreboard includes a deferred buffer start index;
• wherein upon encountering an unresolved data dependency during execution of an instruction, the execution mechanism is configured to perform a checkpointing operation and execute subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred into a deferred buffer, and wherein other non-deferred instructions are executed in program order,
• wherein upon encountering a deferred instruction that depends on a long-latency operation within the long-latency scoreboard, the execution mechanism is configured to update the deferred buffer start index associated with the long-latency operation to point to position in the deferred buffer occupied by the deferred instruction;
• and
• wherein when a long-latency operation returns, the execution mechanism is configured to execute instructions in the deferred buffer starting at the deferred buffer start index for the returning long-latency operation.