Sharing monitored cache lines across multiple cores

A system comprising:

• a first processor core configured to communicate an address range indication identifying an address range that the first processor core is monitoring for an update, wherein the first processor core is configured to communicate the address range indication responsive to executing a first instruction defined to cause the first processor core to monitor the address range for update;
• and
• a second processor core coupled to receive the address range indication and configured, responsive to executing a store operation that updates at least one byte in the address range, to signal the first processing core, and wherein the second processor core is configured to issue one or more coherency communications to coherently perform the store operation;
• and
• wherein the first processor core is coupled to receive the signal from the second processor core prior to receiving the one or more coherency communications issued by the second processor core to coherently perform the store operation, and wherein the first processor core is configured to exit a first state in which the first processor core is awaiting the update in the address range, the first processor core configured to exit the first state responsive to the signal from the second processor core.