Dynamic reconfiguration of cache memory
AssigneeAdvanced Micro Devices, Inc.
InventorsMichael L. Golden, Richard E. Klass
Life of this patent
Estimating the term…
Abstract
In one embodiment, a processing node includes a plurality of processor cores each including a cache memory coupled to a cache monitor unit and to a configuration unit. Each cache monitor unit may be configured to independently monitor a current utilization of the cache memory to which it is coupled and to determine whether the current utilization is below a predetermined utilization value. The configuration unit may selectably disable one or more portions of the cache memory in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.
Claims23
A method for configuring a cache memory of a processor, the method comprising:
- monitoring a current utilization of the cache memory;
- determining whether the current utilization is below a predetermined utilization value;
- and
- selectably disabling one or more portions of the cache memory in response to determining that the current utilization is below the predetermined utilization value.
A method for dynamically configuring a processing node including a plurality of processor cores, each processor core including a cache memory, the method comprising:
- independently monitoring a respective current utilization corresponding to each of the cache memories;
- determining whether the respective current utilization is below a predetermined utilization value;
- in response to determining that the respective current utilization is below the predetermined utilization value selectably disabling one or more portions of the corresponding cache memory.
A processor comprising:
- a cache memory;
- a cache monitor unit coupled to the cache memory and configured to monitor a current utilization of the cache memory and to determine whether the current utilization is below a predetermined utilization value;
- and
- a configuration unit coupled to the cache monitor unit and to the cache memory, wherein the cache configuration unit is configured to selectably disable one or more portions of the cache memory in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.
A processing node comprising:
- a plurality of processor cores each including:
- a cache memory;
- a cache monitor unit coupled to the cache memory, wherein each cache monitor unit is configured to independently monitor a current utilization of the cache memory to which each cache monitor unit is coupled and to determine whether the current utilization is below a predetermined utilization value;
- and
- a configuration unit coupled to the cache monitor unit and to the cache memory, wherein the cache configuration unit is configured to selectably disable one or more portions of the corresponding cache memory to which the configuration unit is coupled in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.
Dependencies are inferred from the claim text.