Ternary CAM with software programmable cache policies
AssigneeLSI Corporation
InventorsSteven M. Emerson, Balraj Singh
Life of this patent
Estimating the term…
Abstract
A circuit comprising a plurality of first line buffers, an arbiter and a cache. The plurality of first line buffers may be configured to communicate on a plurality of first busses. The arbiter may be configured to perform an arbitration among the first line buffers. The cache block may be configured to (i) determine a particular policy of a plurality of policies in response to a first transaction request from one of the first line buffers winning the arbitration and (ii) generate a second transaction request based upon the first transaction request and the particular policy.
Claims20
A circuit comprising:
- a plurality of first line buffers configured to communicate on a plurality of first busses respectively;
- an arbiter configured to perform an arbitration among said first line buffers to access to a particular block;
- a cache block configured to (i) determine a particular policy of a plurality of policies in response to a first transaction request from one of said first line buffers winning said arbitration and (ii) generate a second transaction request on a second bus to access said particular block based upon both said first transaction request and said particular policy;
- and
- a ternary content addressable memory configured to generate said particular policy in response to a first address of said first transaction request.
A method for operating a circuit, comprising the steps of:
- (A) communicating on a plurality of first busses with a plurality of first line buffers respectively;
- (B) performing an arbitration among said first line buffers to access to a particular block;
- (C) determining a particular policy of a plurality of policies in response to a first transaction request from one of said first line buffers winning said arbitration;
- (D) generating a second transaction request on a second bus to access said particular block based upon both said first transaction request and said particular policy;
- and
- (E) generating said particular policy with a ternary content addressable memory in response to a first address of said first transaction request.
An apparatus comprising:
- means for communicating on a plurality of first busses respectively;
- means for performing an arbitration among a plurality of first busses to access to a particular block;
- means for determining a particular policy of a plurality of policies in response to a first transaction request from one of a plurality of first line buffers winning said arbitration;
- means for generating a second transaction request on a second bus to access said particular block based upon both said first transaction request and said particular policy;
- and
- a ternary content addressable memory configured to generate said particular policy in response to a first address of said first transaction request.
Dependencies are inferred from the claim text.