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US 7,257,667 B2Granted
Status register to improve initialization of a synchronous memory
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device in one embodiment can comprise control circuitry to perform an initialization operation on the synchronous memory, and a status register having at least one data bit that can be programmed to indicate if the initialization is being performed. A method of operating a memory system includes initiating an initialization operation on a memory device, and monitoring a memory status register to determine when the initialization operation is completed.
Claims19
A memory system comprising:
- a processor for controlling operation of the system;
- and
- a synchronous flash memory device coupled to the processor and operating in response to the processor, the memory device comprising:
- a synchronous flash memory array for storing data;
- a plurality of redundant memory elements;
- a status register;
- controller circuitry, coupled to the memory array, that is adapted to perform memory operations including an initialization operation that sets a data content of the status register to a first state while the initialization operation is being performed, reads from the non-volatile fuse element locations of at least one redundant memory element, stores the locations of the at least one redundant memory element that was read from in the status register, and sets the content of the status register to a second state when the initialization operation is complete.
4 more elements
A memory system comprising:
- a processor for controlling operation of the system including generating a status register
- read command;
- and
- a non-volatile memory device coupled to the processor and operating in response to the status register read command, the memory device comprising:
- a non-volatile memory array for storing data;
- a plurality of redundant memory elements;
- a plurality of non-volatile fuse elements;
- a status register;
- and
- memory controller circuitry, coupled to the memory array, that is adapted to perform memory operations including an initialization operation that is initiated in response to a VCC level of the system, the controller circuitry adapted to set a first bit of a status register of the flash memory device to a first state when the initialization operation is initiated, during the initialization operation the controller circuitry is adapted to read data stored in the non-volatile fuse elements, store the data read from the non-volatile fuse elements into the status register, set the first bit of the status register to a second state when the initialization operation is complete, and output the contents of the status register on an external connection in response to the status register read command.
7 more elements
A memory system comprising:
- a processor that controls the memory system and generates a status register read command;
- a flash memory device coupled to the processor that performs an initialization operation in response to a reset connection input signal, the device comprising:
- external data connections coupling the device to the processor;
- a memory array for storing data;
- a status register that stores a status;
- non-volatile fuse elements for storing the status in a non-volatile manner;
- and
- a controller that is adapted to set a first bit of the status register to a first state when the initialization operation is initiated, the memory controller further adapted to perform the initialization operation that includes reading data stored in the non-volatile fuse elements and storing the data read from the non-volatile fuse elements into the status register, the controller further adapted to set the first bit of the status register to a second state when the initialization operation is complete, and controller further adapted to output the contents of the status register on the an external connection in response to the status register read command.
5 more elements
Dependencies are inferred from the claim text.