Network switch and components and method of operation

Apparatus comprising:

• a housing;
• a backplane mounted in the housing;
• a plurality of printed circuit board devices mounted in said backplane;
• circuit elements on one of said circuit board devices comprising:
• a control point processor;
• a semiconductor substrate;
• an interface device operatively connected to said control point processor and having:
• a plurality of interface processors formed on said substrate, a number of said processors being at least five;
• internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors;
• internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors;
• and
• a plurality of input/output ports formed on said substrate;
• at least one of said input/output ports connecting said internal data memory with external data memory;
• at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors;
• said control point processor cooperating with said interface device by loading into said instruction memory instructions to be executed by said interface processors in directing the exchange of data between said data exchange input/output ports and the flow of data through said data memory.

Apparatus comprising:

• a printed circuit board device;
• and
• circuit elements mounted on said circuit board device comprising:
• a control point processor;
• and
• an interface device operatively connected to said control point processor and having:
• a semiconductor substrate;
• a plurality of interface processors formed on said substrate, the number of said processors being at least five;
• internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors;
• internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors;
• and
• a plurality of input/output ports formed on said substrate;
• at least one of said input/output ports connecting said internal data memory with external data memory;
• at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors;
• said control point processor cooperating with said interface device by loading into said instruction memory instructions to be executed by said interface processors in directing the exchange of data between said data exchange input/output ports and the flow of data through said data memory.

Apparatus comprising:

• a printed circuit board device;
• and
• circuit elements mounted on said circuit board device comprising:
• a control point processor;
• an interface device operatively connected to said control point processor and having:
• a semiconductor substrate;
• a plurality of interface processors formed on said substrate, a number of said processors being at least five;
• internal instruction memory formed on said substrate and storing instructions accessibly to said interface processors;
• internal data memory formed on said substrate and storing data passing through said device accessibly to said interface processors;
• and
• a plurality of input/output ports formed on said substrate;
• at least one of said input/output ports connecting said internal data memory with external data memory;
• at least two other of said input/output ports exchanging data passing through the interface device with an external network under the direction of said interface processors;
• said control point processor cooperating with said interface device by loading into said instruction memory instructions to be executed by said interface processors in directing the exchange of data between said data exchange input/output ports and the flow of data through said data memory;
• and
• a self routing switching fabric device operatively connected to said interface device and directing data inbound to the apparatus from identifiable addresses to flow outbound from the apparatus to identified addresses.