Phase comparator, clock data recovery circuit and transceiver circuit

A clock data recovery circuit for allowing differences in phase between an input data signal and clock signals to coincide with one another, comprising:

• a phase comparator for inputting the input data signal and the m clock signals and thereby outputting m error signals respectively indicative of differences in phase between a transient edge of the input data signal and transient edges of the respective clock signals and each having a minimum pulse width of (m/2−1)×T or more, and outputting m reference signals each having a pulse width of (m/2)×T;
• a charging pump group having m charging pumps each of which inputs a predetermined one error signal of the m error signals outputted from the phase comparator and a predetermined one reference signal of the m reference signals and thereby outputs a charge current or a discharge current therefrom;
• a loop filter commonly connected to the m respective charging pumps of the charging pump group and for the charging pump group on a time basis to thereby output a dc voltage component;
• a voltage converter for converting the dc voltage component outputted from the loop filter to a predetermined voltage;
• and
• a voltage controlled oscillator for inputting the predetermined voltage outputted from the voltage converter and generating the m clock signals,
• wherein the voltage controlled oscillator outputs the generated m clock signals to the phase comparator,
• the phase comparator outputs m data signals obtained by subjecting predetermined shape processing to the input data signal and one or more clock signals when the phase comparator is brought to a predetermined lock state,
• the input data signal has a cycle of T, and
• the clock signals are m clock signals whose frequencies are expressed in f/m (where f=1/T, and m=2n (where n:
• whole number greater than or equal to 2)) and whose phases are different 2π/m by 2π/m.