Digital clock recovery circuit
AssigneeRambus Inc.
InventorsWilliam J. Dally, John H. Edmondson, Ramin Farjad-Rad
Life of this patent
Estimating the term…
Abstract
A clock recovery circuit includes a sampler for sampling a data signal. Logic determines whether a data edge lags or precedes a clock edge which drives the sampler, and provides early and late indications. A filter filters the early and late indications, and a phase controller adjusts the phase of the clock based on the filtered indications. Based on the filtered indications, a frequency estimator estimates the frequency difference between the data and clock, providing an input to the phase controller to further adjust the phase so as to continually correct for the frequency difference.
Claims26
A clock recovery circuit, comprising:
- a sampler;
- logic to provide first indication indicating whether a data edge in a data signal lags or precedes a clock edge in a clock signal, the clock signal driving the sampler;
- a frequency estimator which, based on the first indication, estimates a frequency difference between the data and clock to provide second indication indicating the frequency difference;
- and
- a phase controller to receive the first and second indications and to adjust the phase of the clock signal based on the first and second indications, the phase controller continually correcting for the frequency difference.
A clock recovery method, comprising:
- sampling, responsive to a clock edge in a clock, a data signal;
- generating first indication indicating whether a data edge lags or leads the clock edge;
- based on the first indication, producing second indication indicating a frequency difference between the data and the clock;
- receiving the first and second indications;
- and
- adjusting the phase of the clock based on the first and second indications.
A clock recovery system, comprising:
- sampling means for sampling, responsive to a clock edge in a clock signal, a data signal;
- logic means for providing first indication indicating whether a data edge lags or leads the clock edge;
- frequency estimator means for estimating, based on the first indication, a frequency difference between the data and the clock, and for producing second indication indicating the frequency difference;
- the phase controller means further adjusting the phase of the clock based on the estimated frequency difference;
- and
- phase controller means for receiving the first and second indications and for adjusting the phase of the clock signal based on the first and second indications.
Dependencies are inferred from the claim text.