Multiple high-speed bit stream interface circuit
AssigneeBroadcom Corporation
InventorAli Ghiasi
Life of this patent
Estimating the term…
Abstract
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB) or the communication ASIC to another communication ASIC. The high-speed bit stream interface includes a line side interface, a board side interface, and a plurality of signal conditioning circuits. The signal conditioning circuits service each of an RX path and a TX path and include a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The clock and data recovery circuit has an adjustable Phase Locked Loop (PLL) bandwidth that is set to correspond to a jitter bandwidth of a serviced high-speed bit stream.
Claims24
A high-speed serial bit stream interface module comprising:
- a line side interface that services a line side media, that receives a line side receive signal, and that transmits a line side transmit signal;
- a board side interface that services a plurality of transmit bit streams and a plurality of receive bit streams;
- at least one multiplexer that multiplexes the plurality of transmit bit streams to produce the line side transmit signal;
- at least one demultiplexer that demultiplexes the line side receive signal to produce the plurality of receive bit streams;
- and
- a plurality of signal conditioning circuits, each of which services a respective bit stream of the plurality of transmit bit streams and the plurality of receive bit streams.
A high-speed serial bit stream interface module comprising:
- a back plane/box interface that services a first plurality of transmit bit streams and a first plurality of receive bit streams;
- a board side interface that services a second plurality of transmit bit streams and a second plurality of receive bit streams;
- at least one demultiplexer that demultiplexes the first plurality of receive bit streams to produce the second plurality of receive bit streams;
- at least one multiplexer that multiplexes the second plurality of transmit bit streams to produce the first plurality of transmit bit streams;
- and
- a plurality of signal conditioning circuits, each of which services a respective bit stream of the first plurality of transmit bit streams and the first plurality of receive bit streams.
Dependencies are inferred from the claim text.