Memory architecture with multiple serial communications ports

A memory device comprising:

• a memory;
• and
• a plurality of ports for accessing the memory of the memory device, each port having a serial communications link for receiving from and transmitting to an accessing device, each port using plesiosynchronous technique to receive symbols and using in-band symbols to transmit data and out-of-band symbols to transmit control information wherein each port includes a line driver with a fixed driver portion and a variable driver portion for DC-balancing.

A memory device comprising:

• a memory that reads and writes data;
• a multiphase clock generator that provides a multiphase clock signal;
• and a plurality of ports, each port for connecting to a serial communications link and for receiving data and control information via the serial communications link using a plesiosynchronous technique, wherein each port uses the generated multiphase clock signal generated by the multiphase clock generator and wherein each port includes a line driver with a fixed driver portion and a variable driver portion for DC-balancing.