Data memory address generation for time-slot interchange switches
AssigneeIntegrated Device Technology, Inc.
InventorsFrank Matthews, Dave MacAdam
Life of this patent
Estimating the term…
Abstract
Time-slot interchange (TSI) switches and a pipelined data memory address generation circuit are provided. The TSI switches and the pipelined data memory address generation circuit include a first pipeline stage that reads data from a connection memory. A second pipeline stage compares the data read from the connection memory to provide a bank selection value. Optionally, a third pipeline stage reads data from a data memory based on the bank selection value and the data read from connection memory. The timing of the pipeline stages may be adjusted such that the duration of the first pipeline stage is extended and the duration of the second pipeline stage shortened.
Claims39
A time-slot interchange switch, comprising:
- a pipelined data memory address generation circuit, the data memory address generation circuit comprising:
- a first pipeline stage that reads data from a connection memory;
- a second pipeline stage that compares the data read from the connection memory to a write pointer location to provide a bank selection value;
- and
- a third pipeline stage that reads data from a data memory based on the bank selection value and the data read from connection memory.
A data memory address generation circuit of a time-slot interchange switch, comprising:
- a connection memory;
- a data memory counter;
- an address comparator that compares a value read from the connection memory with a value from the data memory counter;
- a first register operably associated with the connection memory to store a value read from the connection memory and provide stored connection memory values on subsequent clock cycles to the address comparator;
- a second register operably associated with the first register that stores a value based on the value stored in the first register;
- a data memory address decode circuit operably associated with the second register to receive a value stored in the second register and provide a decoded address to a data memory;
- and
- a bank register operably associated with the address comparator that stores the output of the address comparator and provides the stored value to the data memory.
A method of generating an address for accessing a data memory of a time-slot interchange switch, comprising:
- generating an address for accessing the data memory utilizing at least two pipeline stages, wherein a first of the at least two pipeline stages reads data from a connection memory and a second of the two pipeline stages provides a comparison of the data read from the connection memory;
- and
- wherein the first of the two pipeline stages carries out the steps of:
- storing a connection memory read address in a first register utilizing a first clock;
- decoding the connection memory read address stored in the first register during a period of the first clock to provide a decoded connection memory read address;
- and
- reading data from the connection memory utilizing the decoded connection memory read address during the period of the first clock.
A system for generating an address for accessing a data memory of a time-slot interchange switch, comprising:
- a connection memory;
- and
- means for generating an address for accessing the data memory utilizing at least two pipeline stages, wherein a first of the at least two pipeline stages reads data from the connection memory and a second of the two pipeline stages provides a comparison of the data read from the connection memory;
- and
- wherein the first of the two pipeline stages comprises:
- means for storing a connection memory read address in a first register utilizing a first clock;
- means for decoding the connection memory read address stored in the first register during a period of the first clock to provide a decoded connection memory read address;
- and
- means for reading data from the connection memory utilizing the decoded connection memory read address during the period of the first clock.
A time-slot interchange switch, comprising:
- a connection memory;
- a data memory;
- a connection-to-data memory pipeline having at least first and second stages therein that are synchronized with a clock signal and consecutively traversed during first and second time intervals, the first and second time intervals having a duration greater than T and less than T respectively, where T is a period of the clock signal.
Dependencies are inferred from the claim text.