Page buffer circuit of flash memory device with improved read operation function and method of controlling read operation thereof

A page buffer circuit of a flash memory device including first memory cells connected to first bit line pairs and second memory cells connected to second bit line pairs, the page buffer circuit comprising:

• first page buffers, which are connected to the first bit line pairs, respectively, and execute a read operation or a program operation on the first memory cells at the same time in response to a first bit line control signal, a first bit line select signal and a first control signal;
• second page buffers, which are connected to the second bit line pairs, respectively, and execute a read operation or a program operation on the second memory cells at the same time in response to a second bit line control signal, a second bit line select signal and a second control signal;
• first bit line precharge circuits, which are connected to the first bit line pairs, respectively, and precharge one of a pair of first bit lines connected thereto to a reference voltage level at the same time in response to a first bit line precharge signal in the read operation of the first page buffers;
• and
• second bit line precharge circuits, which are connected to the second bit line pairs, respectively, and precharge one of a pair of second bit lines connected thereto to the reference voltage in response to a second bit line precharge signal in the read operation of the second page buffers,
• wherein the reference voltage is a stable voltage regardless of variation in temperature and/or voltage.

A method of controlling a read operation of a page buffer circuit, comprising:

• allowing a precharge circuit of each of a plurality page buffers, each connected to a pair of bit lines, to precharge a sensing node to a set voltage in response to a precharge control signal;
• allowing each of a plurality bit line precharge circuits, each connected to a pair of bit lines, to precharge one of the pair of bit lines to a reference voltage level in response to a bit line precharge signal;
• allowing a bit line select circuit of each of the page buffers to select one of the pair of bit lines and to connect the selected bit line to the sensing node, in response to a bit line control signal and a bit line select signal;
• and
• allowing a register circuit of each of the page buffers to sense a voltage of the sensing node, store the sensed data therein and output the stored data as read data, in response to a latch control signal, wherein a bit line precharged to the reference voltage level is the selected bit line and the reference voltage is a stable voltage regardless of variation in temperature and/or voltage.

A method of controlling a read operation of a page buffer circuit, comprising:

• allowing a first precharge circuit of each of first page buffers, each connected to a pair of first bit lines, to precharge a first sensing node to a set voltage in response to a first precharge control signal;
• allowing a second precharge circuit of each of second page buffers, each connected to a pair of second bit lines, to precharge a second sensing node to a set voltage in response to a second precharge control signal;
• allowing each of first bit line precharge circuits, each connected to the pair of first bit lines, to precharge one of the pair of first bit lines to a reference voltage level in response to a first bit line precharge signal;
• allowing each of second bit line precharge circuits, each connected to the pair of second bit lines, to precharge one of the pair of second bit lines to a reference voltage level in response to a second bit line precharge signal;
• allowing a first bit line select circuit of each of the first page buffers to select one of the pair of first bit lines and to connect the selected first bit line to the first sensing node, in response to a first bit line control signal and a first bit line select signal;
• allowing a second bit line select circuit of each of the second page buffers to select one of the pair of second bit lines and to connect the selected second bit line to the second sensing node, in response to a second bit line control signal and a second bit line select signal;
• allowing a first register circuit of each of the first page buffers to sense a voltage of the first sensing node, store first sensed data therein and output the stored data as first read data, in response to a first latch control signal;
• and
• allowing a second register circuit of each of the second page buffers to sense a voltage of the second sensing node, store second sensed data therein and output the stored data as second read data, in response to a second latch control signal,
• wherein the first or second bit line that is precharged to the reference voltage level is the selected first or second bit line, and the reference voltage is a stable voltage regardless of variation in temperature and/or voltage.

A method of controlling a read operation of a page buffer circuit, comprising:

• allowing a first bit line precharge circuit of each of first page buffers, each connected to a pair of first bit lines, to precharge one of the pair of first bit lines to a reference voltage level in response to first bit line precharge signals;
• allowing a second bit line precharge circuit of each of second page buffers, each connected to a pair of second bit lines, to precharge one of the pair of second bit lines to a reference voltage level in response to second bit line precharge signals;
• allowing a first precharge circuit of each of the first page buffers to precharge a first sensing node to a set voltage in response to a first precharge control signal;
• allowing a first bit line select circuit of each of the first page buffers to select one of the pair of first bit lines and to connect the selected first bit line to the first sensing node, in response to first bit line control signals and first bit line select signals;
• allowing a first register circuit of each of the first page buffers to sense a voltage of the first sensing node, stores first sensed data therein and output the stored data as first read data, in response to a first latch control signal, when the selected first bit line is connected to the first sensing node;
• allowing a second precharge circuit of each of the second page buffers to precharge a second sensing node to a set voltage in response to a second precharge control signal;
• allowing a second bit line select circuit of each of the second page buffers to select one of the pair of second bit lines and to connect the selected second bit line to the second sensing node, in response to second bit line control signals and second bit line select signals;
• and
• allowing a second register circuit of each of the second page buffers to sense a voltage of the second sensing node, stores second sensed data therein and output the stored data as second read data, in response to a second latch control signal, when the selected second bit line is connected to the second sensing node,
• wherein the first page buffers and the second page buffers are alternately disposed one by one, and when the first bit line select circuit connects the selected first bit line to the first sensing node, the second bit line select circuit separates the selected second bit line from the second sensing node.