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US 7,257,046 B2Granted
Memory data access scheme
AssigneeAtmel Corporation
InventorsJinshu Son, Liqi Wang, Minh V. Le, Philip S. Ng
Life of this patent
Estimating the term…
Abstract
A bitline selection network is composed of a plurality of bitlines and a plurality of global bitlines. The bitlines are grouped into bytes with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline through a bitline select transistor. Each of the bitline select transistors is activated one at a time by a bitline select controller. Activation of each bitline select transistor provides a connection to a source line, which in turn connects to a sense amplifier and a write data loading logic block. The sense amplifier and the write data loading logic block are used in read and write operations respectively.
Claims10
A bitline selection network, the network comprising:
- a plurality of bitlines, said plurality of bitlines coupled to provide access in reading and writing to a plurality of memory cells;
- a plurality of bitline select switches, each of said plurality of bitline select switches is coupled to one of said plurality of bitlines, said plurality of bitline select switches configured to provide at most only a single coupling to a single one of said plurality of bitlines at a time;
- a plurality of bitline select lines, each of said plurality of bitline select lines being coupled to one of said plurality of bitline select switches and is configured to provide independent control of each of said plurality of bitline select switches;
- a plurality of global bitlines, each of said global bitlines being coupled to a subset of said plurality of bitline select switches and configured to provide a common point of coupling to each of said subsets of said plurality of bitline select switches;
- a plurality of bit select switches, each of said bit select switches is coupled to one of said plurality of global bitlines;
- and
- a plurality of bit select lines, each of said plurality of bit select lines coupled to one of said plurality of bit select switches and electrically coupled to said plurality of memory cells in read and write operations.
4 more elements
A bitline selection system, the system comprising:
- a plurality of bitlines, said plurality of bitlines coupled to provide access in reading and writing to a plurality of memory cells;
- a plurality of bitline select switches, each of said plurality of bitline select switches is coupled to one of said plurality of bitlines, said plurality of bitline select switches configured to provide at most only a single coupling to a single one of said plurality of bitlines at a time;
- a bitline select controller, said bitline select controller coupled to said plurality of bitline select switches and configured to activate one of said plurality of bitline select switches at a time;
- a plurality of global bitlines, each of said plurality of global bitlines being coupled to a subset of said plurality of bit lines;
- a plurality of bit select switches, each of said bit select switches is coupled to one of said plurality of global bitlines;
- a bit select controller, said bit select controller coupled to said plurality of bit select switches and configured to activate one of said bit select switches at a time;
- a source line, said source line being coupled to said plurality of bit select switches and configured to provide electrical communication with said plurality of memory cells in read and write operations;
- a write data loading logic block, said write data loading logic block coupled to said source line and configured to write a data content used in a write operation;
- and
- a sense amplifier, said sense amplifier coupled to said source line and configured to acquire a content of a memory cell in a read operation.
7 more elements
A bitline selection apparatus, the apparatus comprising:
- an amplification means for accepting an input signal and providing an output signal;
- a writing means for writing an input signal and providing an output programming signal;
- a bitline selection means for selecting one of a plurality of bitline signals as an input signal to one of a plurality of global bitlines;
- a bitline addressing means for controlling selection of one of a plurality of bitline signals at a time, the plurality of bitline signals conveying a number of unique instances of bitlines equal in number to the plurality of bitline selection means;
- a bit selection means for either selecting one of a plurality of global bitline signals as input to said amplification means or for selecting said output signal of said writing means as an input programming signal to a plurality of storage locations;
- and
- a bit addressing means for controlling selection of one of a plurality of global bitline signals at a time, the plurality of global bitline signals conveying a number of unique instances of said global bitlines equal in number to the plurality of bit selection means.
4 more elements
A method of selecting a bitline, the method comprising:
- receiving a byte select signal;
- receiving a bit select signal;
- combining said byte select signal and said bit select signal;
- producing a selection signal;
- selecting a single bitline at a time;
- and
- accessing a bitline once in a memory device read or write operation.
4 more elements
Dependencies are inferred from the claim text.