Uni-stage delay speculative address decoder

A method for decoding an address, the method comprising:

• conveying 2n bits to an address decoder, wherein half of the 2n bits represent address signals of an n-bit address, and wherein half of the 2n bits represent complements of the address signals;
• performing a first logic function on n−1 bits of a combination of n bits for each of the plurality of bit slices, wherein the combination of n bits is unique for each of the plurality of bit slices with respect to other ones of the plurality of bit slices, and wherein the first logic function provides a first output signal;
• performing a second logic function for each of the plurality of bit slices, wherein the second logic function is performed on the first output signal and one of the n bits, wherein the second logic function produces a second output signal;
• performing a third logic function for each of the plurality of bit slices wherein the third logic function is performed on the first output signal and a complement of the one of the n bits, wherein the third logic function produces a third output signal;
• and
• providing an address selection output by asserting one of the second or third output signal for one of the plurality of bit slices, wherein the address selection output corresponds to the n-bit address.