Isolation device over field in a memory device
AssigneeMicron Technology, Inc.
InventorsLuan C. Tran, Stephen R. Porter, Scot M. Graham, Steven E. Howell
Life of this patent
Estimating the term…
Abstract
A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.
Claims36
A method comprising:
- accessing data in a first storage node of a memory cell of a memory device;
- and
- applying a positive voltage to a gate of an isolation device, the isolation device being located between the first storage node and a second storage node of the memory device for isolating the first storage node from the second storage node.
A method comprising:
- accessing data in a first storage node of a memory cell of a memory device;
- applying a non-ground potential to a gate of an isolation device, the isolation device being located between the first storage node and a second storage node of the memory device for preventing conductivity between the first and second storage nodes, the isolation device being in an inactive state during the applying of the non-ground potential;
- and
- controlling a current on a path between the gate of the isolation device and a power node.
A method comprising:
- activating a first access transistor to access data in a first storage node of a first memory cell of a memory device;
- activating a second access transistor to access data in a second storage node of a second memory cell of the memory device;
- and
- applying a positive voltage to a gate of an isolation device, the isolation device being located between the first and second storage nodes, and the isolation device being in an inactive state during the applying of the positive voltage.
A method comprising:
- activating a first access transistor to access data in a first storage node of a first memory cell of a memory device;
- activating a second access transistor to access data in a second storage node of a second memory cell of the memory device;
- applying a non-ground voltage to a gate of an isolation device, the isolation device being located between the first and second storage nodes;
- and
- modifying a resistance of a path between a power node and the gate of the isolation device.
A method comprising:
- transferring data between a processor and at least one storage node of a memory cell of a memory device;
- and
- applying a positive voltage to a gate of an isolation device, the isolation device being located between the first storage node and a second storage node of the memory device for isolating the first storage node from the second storage node.
Dependencies are inferred from the claim text.