Enhanced sensing in a hierarchical memory architecture

A memory circuit, comprising:

• a plurality of word lines;
• a plurality of pairs of complementary bank bit lines;
• a plurality of block select lines;
• and
• a plurality of block circuits, each of the block circuits comprising:
• a local bit line;
• a first transistor including a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source supplying a first voltage;
• a second transistor including a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line;
• a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit;
• and
• a plurality of sense amplifier circuits, each sense amplifier circuit comprising:
• a precharge circuit adapted for connection to a corresponding pair of complementary bank bit lines, the precharge circuit being operative to selectively drive the pair of complementary bank bit lines to a second voltage in response to a first control signal;
• a latch circuit adapted for connection to the corresponding pair of complementary bank bit lines;
• and
• a replication circuit adapted for connection to the corresponding pair of complementary bank bit lines, the replication circuit being operative to selectively transfer a voltage representative of a logic state on a first bank bit line of the corresponding pair of complementary bank bit lines to a second bank bit line of the corresponding pair of complementary bank bit lines in response to at least a second control signal.

An integrated circuit including at least one sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit, the at least one sense amplifier circuit comprising:

• a precharge circuit adapted for connection to a pair of complementary bit lines corresponding to the selected memory cell, the precharge circuit being operative to selectively drive the pair of complementary bit lines to a first voltage in response to a first control signal;
• a latch circuit adapted for connection to the pair of complementary bit lines;
• and
• a replication circuit adapted for connection to the pair of complementary bit lines, the replication circuit being operative to selectively transfer a voltage representative of a logic state on a first bit line of the pair of complementary bit lines to a second bit line of the pair of complementary bit lines in response to at least a second control signal, wherein the replication circuit comprises:
• a first switch circuit adapted for connection between the first bit line and a second voltage source supplying a second voltage, the first switch circuit including a first input adapted for receiving the second control signal and a second input adapted for connection to the second bit line;
• and
• a second switch circuit adapted for connection between the second bit line and the second voltage source, the second switch circuit including a first input adapted for receiving a third control signal and a second input adapted for connection to the first bit line.