Memory circuit and related method for integrating pre-decoding and selective pre-charging
AssigneeVIA Technologies, Inc.
InventorsChi-Ting Cheng, Po-Yo Tseng
Life of this patent
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Abstract
In a memory circuit, memory cells are arranged in a matrix by “row line-and column line” (may also denoted as “word line and bit line”). The invention provides a memory circuit and related method capable for independently pre-charging the column lines or bit lines selectively during data accessing according to results of column pre-decoding to decrease the pre-charging power consumption. After pre-charging, the objective memory cell is enabled to change or not to change the corresponding electric level of the connected column line according to the stored data, and a sense amplifier detects the stored data by measuring the electric level of the column line.
Claims16
A memory circuit comprising:
- a plurality of memory cells for respectively storing data;
- a plurality of column lines for respectively connecting at least one memory cell;
- a plurality of pre-charge units, each pre-charge unit corresponds to one of the column lines, when one of the pre-charge unit is enabled, the pre-charge unit charges the corresponding column line;
- when the pre-charge unit is disabled, the pre-charge unit stops charging the corresponding column line;
- a column pre-decoder, providing a corresponding selection signal for each column line to indicate whether the column line is connected to a objective memory cell when the objective memory cell is to be accessed;
- a sense amplifier, electrically connected to the objective memory cell for receiving and sensing the stored data;
- a plurality of control units, respectively corresponding to one of the column lines, for respectively receiving the corresponding selection signal and enabling or disabling the corresponding pre-charge unit according to the corresponding selection signal, so that the pre-charge units are independently and respectively enabled or disabled according to whether the column line is connected to the objective memory cell;
- and
- a plurality of accessing units disposed between the column lines and the sense amplifier, wherein each accessing unit is enabled to be conducted or is disabled to be not conducted, and one of the column lines is electrically connected to the sense amplifier only when all the accessing units corresponding to the column line are conducted;
- wherein the column pre-decoder records the corresponding decision signal to determine whether the accessing units corresponding to the column lines should be enabled or disabled.
A memory circuit comprising:
- a plurality of memory cells for forming a matrix by a plurality of column lines and a plurality of row lines, wherein each column line has a corresponding pre-charge unit and a corresponding control unit, the control unit controls the pre-charge unit to pre
- charge or not to pre charge the corresponding column line;
- a column pre-decoder for providing a selection signal corresponding to one of the column lines;
- and
- a multiplex module comprising a multi-level accessing module connected to the column line, wherein the multiplex module receives the selection signal, and determines to pre charge or not to pre charge the column line according to the selection signal.
A method for pre-charging a memory circuit, wherein the memory circuit comprises a plurality of column lines, each column line is respectively connected to at least one memory cell, and each column line is electronically connected to a sense amplifier through at least one low-level accessing unit and at least one high-level accessing unit that are independently enabled and disabled;
- the method comprising:
- asserting selection signals;
- independently enabling or disabling the low-level accessing unit and the high-level accessing unit according to the selection signals;
- and
- pre-charging the column line when the low-level accessing unit and the high-level accessing unit of the column line are both enabled.
A memory circuit comprising:
- a plurality of memory cells for respectively storing data;
- a plurality of column lines for respectively connecting at least one memory cell;
- a row decoder for selectively enabling memory cells;
- a master module for providing a pre-charge signal;
- a plurality of pre-charge units, each pre-charge unit corresponds to one of the column lines, when one of the pre-charge unit is enabled, the pre-charge unit charges the corresponding column line;
- when the pre-charge unit is disabled, the pre-charge unit stops charging the corresponding column line;
- a column pre-decoder, providing a corresponding selection signal for each column line to indicate whether the column line is connected to a objective memory cell when the objective memory cell is to be accessed;
- and
- a plurality of control units, respectively corresponding to one of the column lines, for respectively receiving the corresponding selection signal and enabling or disabling the corresponding pre-charge unit according to the corresponding selection signal, so that the pre-charge units are independently and respectively enabled or disabled according to whether the column line is connected to the objective memory cell;
- wherein when accessing the objective memory cell, the master module firstly provides the disabling pre-charge signal;
- after the column pre-decoder provides the selection signals, the master module then provides the enabling pre-charge signal, and then the row decoder enables the objective memory cell so that the stored data is transmitted to the corresponding connected column line.
Dependencies are inferred from the claim text.