Bit line discharge control method and circuit for a semiconductor memory
AssigneeSTMicroelectronics S.r.l.
InventorsFerdinando Bedeschi, Claudio Resta, Roberto Gastaldi
Life of this patent
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Abstract
A method of controlling a discharge of bit lines of a matrix of memory cells comprises conditioning a value of a current flowing through a bit line of the matrix during a bit line discharge phase to an absence of an indication of defectiveness of the bit line. The method allows preventing crowbar currents that otherwise flow during the bit line discharge phase when a defective bit line exhibits a short-circuit to a defective word line.
Claims43
A method of controlling a discharge of bit lines of a matrix of memory cells, comprising
- controlling a value of a current flowing through a bit line of the matrix during a bit line discharge phase in response to an indication that the bit line is defective.
A circuit for controlling a discharge of bit lines of memory cells in a memory matrix, comprising:
- bit line discharge means, associated with the bit limes, activatable in a bit line discharge operating phase of the memory for enabling a discharge of bit line capacitances associated with the bit lines, comprising
- bit line current control means, controllable for at least limiting a current flowing through one of the bit lines in the bit line discharge operating phase in response to an indicating that the one bit line is defective.
A semiconductor memory, including at least one matrix of memory cells, matrix word lines, a word line driver circuit associated with each word line for driving the word line, matrix bit lines and, associated with each bit line, a bit line discharge circuit, wherein
- a controlled current-limiting arrangement is provided in a circuit path associated with a word line and bit line pair and including one of the word line driver circuits driving the word line of the pair, the associated word line, one of the bit lines and the associated bit line discharge circuit,
- said current limiting arrangement being capable of at least limiting a current flowing through the circuit path in response to an indication of defectiveness of at least one among the word line and the bit line of the pair.
A memory, comprising:
- a bit line;
- a redundancy circuit operable to indicate that the bit line is defective;
- and
- a discharge circuit coupled to the bit line and to the redundancy circuit and operable to limit a discharge current flowing through the bit line to a first predetermined value in response to the redundancy circuit.
A memory, comprising:
- a word line;
- a redundancy circuit operable to indicate that the word line is defective;
- and
- a driver coupled to the word line and to the redundancy circuit and operable to drive the word line with a drive current and to limit the drive current to a first predetermined value in response to the redundancy circuit.
An electronic system, comprising:
- a memory having,
- a bit line,
- a redundancy circuit operable to indicate that the bit line is defective, and
- a discharge circuit coupled to the bit line and to the redundancy circuit and operable to limit a discharge current flowing through the bit line to a first predetermined value in response to the redundancy circuit.
An electronic system, comprising:
- a memory having,
- a word line,
- a redundancy circuit operable to indicate that the word line is defective, and
- a driver coupled to the word line and to the redundancy circuit and operable to drive the word line with a drive current and to limit the drive current to a first predetermined value in response to the redundancy circuit.
A method, comprising:
- discharging a bit line;
- and
- limiting a discharge current through the bit line to a predetermined value if the bit line is defective.
A method, comprising:
- discharging a first bit line with a first discharge current;
- discharging a second bit line with a second discharge current such that the second discharge current is limited to a predetermined level that is lower than a level to which the first discharge current is limited;
- and
- accessing a memory cell coupled to the first bit line after discharging the first and second bit lines.
A method, comprising:
- driving a word line;
- and
- limiting a drive current through the word line to a predetermined value if the word line is defective.
A method of accessing memory cells in a memory cell matrix having a plurality of matrix word lines and a plurality of matrix bit lines, wherein said accessing includes selecting a matrix word line and at least one matrix bit line, the method comprising:
- before selecting a specified matrix word line:
- keeping the plurality of matrix word lines at a predetermined deselection potential higher than a reference potential;
- keeping the plurality of matrix bit lines floating;
- discharging the matrix bit lines to the reference potential,
- bringing the selected word line to the reference potential, and
- bringing the selected bit line to a potential that depends on an operation to be performed on the accessed memory cell, wherein said discharging includes limiting a value of a current flowing through a bit line of the matrix during the bit line discharge phase in response to an indication of defectiveness of the bit line.
A semiconductor memory including at least one matrix of memory cells having a plurality of word lines and a plurality of bit lines, the semiconductor memory comprising:
- word line selection circuits and bit line selection circuits for selecting the word lines and the bit lines respectively, wherein before a specified matrix word line is selected the word line selection circuits are adapted to keep the plurality of matrix word lines at a predetermined deselection potential higher than a reference potential, and the bit line selection circuits are adapted to keep the plurality of matrix bit lines floating, the word line selection circuits being further adapted to bring the selected word line to the reference potential, and the bit line selection circuits being further adapted to bring the selected bit line to a potential that depends on an operation to be performed on the accessed memory cell;
- a circuit for controlling a discharge of bit lines of memory cells in a memory matrix, comprising:
- bit line discharge means, associated with the bit lines, activatable in a bit line discharge operating phase of the memory before the word line selection circuits brings the selected word line to the reference potential for enabling a discharge to the reference potential of bit line capacitances associated with the bit lines, and bit line current control means, controllable for at least limiting a current flowing through one of the bit lines during the bit line discharge operating phase in response to an indication that the one of the bit lines is defective.
Dependencies are inferred from the claim text.