Minimizing adjacent wordline disturb in a memory device
AssigneeMicron Technology, Inc.
InventorsPaul J. Rudeck, Andrei Mihnea, Andrew Bicksler
Life of this patent
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Abstract
A selected wordline that is coupled to cells for programming is biased with a programming voltage. The unselected wordlines that are adjacent to the selected wordline are biased at a first predetermined voltage. The remaining wordlines are biased at a second predetermined voltage that is greater than the first predetermined voltage. The first predetermined voltage is selected by determining what unselected, adjacent wordline bias voltage produces a minimized Vpass disturb in response to the selected wordline programming voltage.
Claims17
A method for minimizing adjacent wordline disturb while programming at least one cell in an array of memory cells that are arranged in rows and columns, each row coupled by a wordline and each column coupled by a bitline, the method comprising:
- biasing a selected wordline with a programming voltage, the selected wordline coupled to the at least one memory cell;
- and
- biasing unselected wordlines adjacent to the selected wordline at a first predetermined voltage and remaining wordlines at a second predetermined voltage that is greater than the first predetermined voltage wherein the programming voltage is increased over a time period by a predetermined step voltage and the first predetermined voltage is decreased over the time period by a predetermined fraction of the predetermined step voltage.
A method for minimizing adjacent wordline disturb while programming at least one memory cell in a NAND array of memory cells arranged in rows and columns, each row coupled by a wordline and each column coupled by a bitline, the method comprising:
- biasing a selected wordline with a programming voltage, the selected wordline coupled to at least one memory cell to be programmed;
- biasing, at a first predetermined voltage, unselected wordlines adjacent to the selected wordline;
- biasing, at a second predetermined voltage, unselected wordlines that are not adjacent to the selected wordline, wherein the second predetermined voltage is greater than the first predetermined voltage;
- and
- ramping up the programming voltage on the selected wordline over a period of time while the first predetermined voltage is ramped down over the period of time.
A flash memory device comprising:
- a memory cell array arranged in rows and columns, each row of cells coupled by a wordline and each column of cells coupled by a bitline;
- control circuitry for controlling biasing of the wordlines during a program operation wherein the control circuitry is adapted to set a program voltage on a selected wordline and is adapted to set a predetermined voltage on unselected wordlines that are adjacent to the selected wordline, the predetermined voltage being less than a voltage that biases unselected wordlines that are not adjacent to the selected wordline;
- wherein the programming voltage on the selected wordline is ramped up over a period of time and the predetermined voltage is ramped down over the period of time.
Dependencies are inferred from the claim text.