Hybrid non-volatile memory device

A non-volatile memory device comprising:

• a first memory cell array for storing one or more codes;
• a second memory cell array for storing one or more data, which are updated more frequently than the codes, the second memory cell array enduring substantially more programming cycles than the first memory cell array;
• and
• a third memory cell array for storing address mapping information that indicates one or more locations of one or more memory cells in the second memory cell array,
• wherein a memory cell in the second memory cell array occupies a larger area than a memory cell in the first memory cell array does.

A micro-processing system comprising:

• a controller for outputting one or more data associated with one or more logical addresses;
• a non-volatile memory device having a first memory cell array for storing one or more codes, a second memory cell array for storing the data, which are updated more frequently than the codes, and a third memory cell array for storing address mapping information that indicates one or more physical locations of one or more memory cells in the second memory cell array;
• a volatile memory device coupled with the non-volatile memory device for temporarily storing the address mapping information retrieved from the third memory cell array;
• and
• a comparator coupled among the controller, the volatile memory device and the non-volatile memory device for storing the data received from the controller to the second memory cell array based on the address mapping information forwarded by the volatile memory device,
• wherein the second memory cell array endures substantially more programming cycles than the first memory cell array does.