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US 7,257,017 B2Granted
SRAM cell for soft-error rate reduction and cell stability improvement
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy Liaw
Life of this patent
Estimating the term…
Abstract
An SRAM device includes a memory cell. The memory cell includes a first cross-coupled inverter and a second cross-coupled inverter, which is electrically connected to the first cross-coupled inverter. Each inverter includes a pull down device and a pull up device. The pull up device is electrically connected to the pull down device. A channel width ratio of the pull up device to the pull down device is preferably within a range of about 1.5 to about 0.8. A channel area ratio of the pull up device to the pull down device is preferably within a range of about 3 to about 1. A pass gate device is electrically connected to the pull down device. A channel width ratio of the pull up device to the pass gate device is preferably within a range of about 3.0 to about 1.2.
Claims54
An SRAM device comprising:
- a memory cell comprising
- a substrate;
- a first cross-coupled inverter;
- and
- a second cross-coupled inverter, wherein an output node of said first cross-coupled inverter is electrically connected to an input node of said second cross-coupled inverter, wherein an output node of said second cross-coupled inverter is electrically connected to an input node of said first cross-coupled inverter, and wherein each inverter comprises
- a pull down device, and
- a pull up device formed at least partially within the substrate, wherein a drain node of said pull down device is electrically connected to a drain node of said pull up device, and wherein a channel width ratio of said pull up device to said pull down device is within a range of about 1.5 to about 0.8.
4 more elements
An SRAM device comprising:
- a memory cell comprising
- a substrate;
- a first cross-coupled inverter;
- a second cross-coupled inverter, wherein an output node of said first cross-coupled inverter is electrically connected to an input node of said second cross-coupled inverter, wherein an output node of said second cross-coupled inverter is electrically connected to an input node of said first cross-coupled inverter via a storage node, and wherein each inverter comprises
- a pull down device;
- and
- a pull up device having a source and drain region located at least partially within the substrate, wherein a drain node of said pull down device is electrically connected to a drain node of said pull up device;
- and
- a pass gate device electrically connected to said pull down device, wherein a channel width ratio of said pull up device to said pass gate device is within a range of about 3 to about 1.2.
6 more elements
A method of manufacturing an SRAM device comprising:
- forming a memory cell, wherein said forming of said memory cell comprises
- forming a first cross-coupled inverter, and
- forming a second cross-coupled inverter so that said second cross-coupled inverter is electrically connected to said first cross-coupled inverter by a storage node, wherein said forming each of said inverters comprises
- forming a pull down device, and
- forming a pull up device so that said pull up device is electrically connected to said pull down device, and so that a channel width ratio of said pull up device to said pull down device is within a range of about 1.5 to about 0.8.
2 more elements
A method of manufacturing an SRAM device comprising:
- forming a memory cell, wherein said forming of said memory cell comprises
- forming a first cross-coupled inverter, and
- forming a second cross-coupled inverter so that said second cross-coupled inverter is electrically connected to said first cross-coupled inverter by a storage node, wherein said forming each of said inverters comprises
- forming a pull down device, and
- forming a pull up device so that said pull up device is electrically connected to said pull down device, wherein a channel area ratio of said pull up device to said pull down device is within a range of about 3 to about 1.
2 more elements
A method of manufacturing an SRAM device comprising the steps of:
- forming a memory cell comprising
- forming a first cross-coupled inverter, and
- forming a second cross-coupled inverter electrically connected to said first cross-coupled inverter by a storage node, wherein each inverter comprises a pull down device, and
- forming a pass gate device electrically connected to said pull down device by a storage node, wherein a channel width ratio of said pull up device to said pass gate device is within a range of about 3 to about 1.2.
1 more element
A method of manufacturing an SRAM device comprising the steps of:
- forming a memory cell comprising
- forming a first cross-coupled inverter;
- forming a second cross-coupled inverter electrically connected to said first cross-coupled inverter, wherein each inverter comprises a pull down device;
- and
- forming a pass gate device electrically connected to said pull down device by a storage node, wherein a channel area ratio of said pull up device to said pass gate device is within a range of about 3.5 to about 1.25.
2 more elements
An SRAM device comprising:
- a memory cell comprising
- a first cross-coupled inverter,
- a second cross-coupled inverter electrically connected to said first cross-coupled inverter, wherein each inverter comprises
- a pull down device, and
- a pull up device electrically connected to said pull down device, and
- a pass gate device electrically connected to said pull down device, wherein a channel width ratio of said pull up device to said pull down device is within a range of about 1.5 to about 0.8, and wherein a channel width ratio of said pull up device to said pass gate device is within a range of about 3.0 to about 1.2.
3 more elements
An SRAM device comprising:
- a memory cell comprising
- a first cross-coupled inverter, and
- a second cross-coupled inverter electrically connected to said first cross-coupled inverter, wherein each inverter comprises
- a pull down device, and
- a pull up device electrically connected to said pull down device,
- a pass gate device electrically connected to said pull down device, wherein a channel area ratio of said pull up device to said pull down device is within a range of about 3 to about 1, and wherein a channel area ratio of said pull up device to said pass gate device is within a range of about 3.5 to about 1.25.
3 more elements
An SRAM device comprising:
- a memory cell comprising
- a first cross-coupled inverter, and
- a second cross-coupled inverter electrically connected to said first cross-coupled inverter, wherein each inverter comprises
- a pull down device, and
- a pull up device electrically connected to said pull down device,
- a pass gate device electrically connected to said pull down device, wherein a channel width ratio of said pull up device to said pull down device is within a range of about 1.5 to about 0.8, wherein a channel width ratio of said pull up device to said pass gate device is within a range of about 3.0 to about 1.2, wherein a channel area ratio of said pull up device to said pull down device is within a range of about 3 to about 1, and wherein a channel area ratio of said pull up device to said pass gate device is within a range of about 3.5 to about 1.25.
3 more elements
Dependencies are inferred from the claim text.