Semiconductor memory device having a floating storage bulk region

A semiconductor memory device including a plurality of transistors, wherein each of the transistor comprises:

• a semiconductor layer which is a first conduction type and electrically isolated from other memory cells such that is floating;
• a drain diffusion region which is a second conduction type, formed in the first conduction-type semiconductor layer, and connected to a bit line;
• a source diffusion region which is the second conduction type, formed apart from the drain diffusion region in the first conduction-type semiconductor layer, and connected to a source line;
• and
• a gate electrode formed on the semiconductor layer between the drain diffusion region and the source diffusion region with a gate insulator therebetween, and forms a word line,
• wherein the transistor has a first data state having a first threshold voltage in which excessive majority carriers are held in the semiconductor layer and a second data state having a second threshold voltage in which the excessive majority carriers in the semiconductor layer are emitted,
• wherein the bit line is one of a plurality of bit lines, sense amplifier being provided for the plurality of bit lines, one of the bit lines being selected to be connected to the sense amplifier
• wherein a voltage of the source line is constant, and
• wherein when data is written, with the source line as a reference voltage,
• a first voltage higher than the reference voltage is given to the word line of a selected one of the transistors,
• a second voltage lower than the reference voltage is given to the word line of a non-selected one of the transistors,
• a third voltage higher than the reference voltage is given to the bit line when the first data state is written, and
• a fourth voltage lower than the reference voltage is given to the bit line when the second data state is written.

A semiconductor memory device comprising:

• an SOI substrate in which a silicon layer is form on an insulating film form an silicon substrate;
• a plurality of transistor which have drain diffusion regions and source diffusion regions form in the silicon layer and gate electrodes formed on the silicon layer, wherein pairs of the transistors, each pair sharing one of the drain diffusion regions, being arranged in a matrix form an element-isolated in a channel width direction, wherein the gate electrodes of the transistors arranged in a first direction are continuously formed so as to form word line;
• and
• a plurality of bit lines running in a second direction intersecting the first direction and connected to a drain diffusion regions of the transistors;
• wherein each of the transistors has a first data state having a first threshold voltage in which excessive majority carries are held in the silicon layer and a second data state having a second threshold voltage in which the excessive majority carries in the silicon layer are emitted,
• wherein a sense amplifier is provided for the plurality of bit lines, one of the bit lines being selected to be connected to the sense amplifier,and
• wherein the first data state is a state in which impact ionization is generated near a drain junction by operating the transistor and in which excessive majority carriers produced by this impact ionization are held in the silicon layer, and the second data state is a state in which a forward bias is applied between the silicon layer and the drain diffusion region to extract the excessive majority carriers from within the silicon layer to the drain diffusion region.