Semiconductor memory having twisted bit line architecture
AssigneeKabushiki Kaisha Toshiba
InventorsTadashi Miyakawa, Daisaburo Takashima
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Abstract
A semiconductor memory according to an example of the present invention comprises first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns, a first cell block which is disposed in the first column, a first block select transistor which is connected between the first or second bit line and one end of the first cell block, a second cell block which is disposed in the second column, and a second block select transistor which is connected between the second or first bit line and one end of the second cell block.
Claims20
A semiconductor memory comprising:
- first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns;
- a first cell block which is disposed in the first column;
- a first block select transistor which is connected between the first or second bit line and one end of the first cell block;
- a second cell block which is disposed in the second column;
- and
- a second block select transistor which is connected between the second or first bit line and one end of the second cell block,
- wherein the twisting of the first and second bit lines is carried out at a block selector region in which the first and second block select transistors are disposed.
A semiconductor memory comprising:
- first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns;
- a first cell block which is disposed in the first column;
- a first block select transistor which is connected between the first or second bit line and one end of the first cell block;
- a first plate line which is connected to the other end of the first cell block;
- a second cell block which is disposed in the second column;
- a second block select transistor which is connected between the second or first bit line and one end of the second cell block;
- and
- a second plate line which is connected to the other end of the second cell block,
- wherein the twisting of the first and second bit lines is carried out at a plate line region in which the first and second plate lines are disposed.
A semiconductor memory comprising:
- first and second bit lines having a twisted bit-line architecture in which the first and second bit lines are alternately twisted at a constant period in first and second columns;
- a plurality of first memory cells which are disposed in the first column;
- and
- a plurality of second memory cells which are disposed in the second column,
- wherein the first bit line is only connected to said plurality of first memory cells, and the second bit line is only connected to said plurality of second memory cells.
Dependencies are inferred from the claim text.