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US 7,256,761 B2Granted
Scanner integrated circuit
AssigneeChunghwa Picture Tubes, Ltd.
InventorsJuin-Ying Huang, Shih-Hsiung Huang, Wen-Tse Tseng
Life of this patent
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Abstract
A scanner integrated circuit comprises a gate integrated circuit including a shift register, a delay unit, a voltage detecting unit and a logic unit for achieving an output enable function so that the integrated circuit can reduce the pin numbers and the package volume and decrease the chip cost.
Claims7
A scanner integrated circuit comprising an output enable circuit in a gate IC, wherein said output enable circuit comprises:
- a shift register receiving a vertical clock signal and generating a first signal;
- a delay unit revived from said first signal and being generated a second signal by delaying said first signal;
- a voltage detecting unit filtering said second signal to get a third signal;
- and
- a logic unit for comparing said first and third signals, outputting an output signal after logic operation,
- wherein said output enable circuit in a gate IC being inputted a start vertical signal to start by a timing controller;
- and said output enable circuit receiving a vertical clock signal from said timing controller to generate an output signal,
- wherein the shift register is directly connected with the delay unit.
5 more elements
Dependencies are inferred from the claim text.