US 7,256,725 B2Granted

Resistor ladder interpolation for subranging ADC

AssigneeBroadcom Corporation

InventorJan Mulder

Life of this patent

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Abstract

An analog to digital converter includes a resistive ladder outputting a plurality of reference voltages and a coarse ADC receiving the reference voltages and a voltage input. A plurality of coarse comparators receive an output of the coarse ADC. A switch matrix receives an output of the coarse ADC and the reference voltages. The switch matrix inputs a plurality of control signals for selecting at least two voltage subranges. A fine ADC receives the two voltage subranges and the voltage input. A plurality of fine comparators receive an output of the fine ADC. An encoder converts outputs of the coarse and fine comparators to a digital representation of the voltage input. The voltage subranges are adjacent. Each control signal includes a plurality of control lines for controlling corresponding switches. The switches are field effect transistors.

Claims5

Dependent claims

An autozero amplifier comprising:

a positive input terminal;
a negative input terminal;
a first capacitor connected to said positive input terminal;
a second capacitor connected to said negative input terminal;
a first pair of transistors with their corresponding drains connected to the first capacitor at a common node
wherein the source of a first transistor of said first pair of transistors is connected to a positive threshold voltage,
the source of a second of said first pair of transistors is connected to a positive voltage terminal of a resistor ladder,
and
the gates said first pair of transistors are connected to a non-overlapping two-phase clock;
and
a second pair of transistors with their drains connected to the second capacitor at a common node
wherein the source of a first of said second pair of transistors is connected to a negative threshold voltage,
the source of a second of said second pair of transistors is connected to a negative voltage terminal of said resistor ladder,
and
the gates said second pair of transistors are connected to said non-overlapping two-phase clock.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/651,454Filed 10 Jan 2007 · division
Priority: 24 May 2002
Published: US 2007/0109173 A117 May 2007
Granted: 14 Aug 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H03K 17/04106
Without feedback from the output circuit to the control circuit: in field-effect transistor switches
H03F 3/45183
Using MOSFET transistors as the active amplifying circuit: long tailed pairs
H03F 3/45632
Characterised by the way of common mode signal rejection: in differential amplifiers with FET transistors as the active amplifying circuit
H03M 1/204
Using an analogue interpolation circuit: in which one or more virtual intermediate reference signals are generated between adjacent original…

Family

Application10/153,709Parent of this continuation-in-part · filed 24 May 2002
Application10/158,774Parent of this continuation · filed 31 May 2002
US 6,628,224 B1Parent of this continuation-in-part · filed 30 Sep 2003
Application10/748,250Parent of this continuation-in-part · filed 31 Dec 2003
US 6,697,005 B2Parent of this continuation · filed 24 Feb 2004
Application10/926,407Parent of this continuation-in-part · filed 26 Aug 2004
US 6,784,818 B2Parent of this continuation-in-part · filed 31 Aug 2004
Application11/084,236Parent of this division · filed 21 Mar 2005
US 2007/0109173 A1Pre-grant publication · published 17 May 2007
US 7,190,298 B2Parent of this division
Application11/084,236Parent of this continuation-in-part
Application10/748,250Parent of this continuation
Application10/158,774Parent of this continuation-in-part
US 2003/0218557 A1Published application
US 2004/0150544 A1Published application
US 2005/0068216 A1Published application
US 2005/0162299 A1Published application
US 7,271,755 B2Related patent
US 7,256,725 B2This patent

From the US filing history. Foreign family members aren’t listed.