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US 7,256,719 B2Granted
Digital data decompression implemented in a field programmable array device
AssigneeInternational Business Machines Corporation
InventorsJoan L. Mitchell, Phillip K. Hoskins
Life of this patent
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Abstract
Operations for decompression of compressed data is performed in parallel and in a pipelined manner to generate addresses into a memory on-the-fly rather than using a large look-up table. The logic circuits for doing so are thus reduced to the point of being able to be formed by suitable programming of a field programmable gate array (FPGA) while achieving substantial increase in processing speed beyond speed increases attributable to increase of clock rates.
Claims20
Apparatus comprising
- a field programmable gate array (FPGA) programmed to form components for performing steps of
- receiving an input stream of bits,
- performing a comparison to determine code word length,
- performing an addition of an offset and a number of bits of said bit stream in parallel with said step of performing a comparison,
- selecting a result of said step of performing an addition, and
- discarding a number of bits of said bit stream equal to said length of said code word upon completion of said step of performing a comparison.
3 more elements
A method of decompressing compressed data, said method including steps of
- receiving an input stream of bits,
- performing a comparison to determine code word length,
- performing an addition of an offset and a number of bits of said bit stream in parallel with said step of performing a comparison,
- selecting a result of said step of performing an addition, and
- discarding a number of bits of said bit stream equal to said length of said code word upon completion of said step of performing a comparison.
2 more elements
Dependencies are inferred from the claim text.