All-digital phase-locked loop
AssigneeRealtek Semiconductor Corp.
InventorShiao-Yang Wu
Life of this patent
Estimating the term…
Abstract
An all-digital phase-locked loop (ADPLL) includes: a digital phase frequency detector (PFD) for generating a detection signal by detecting frequency difference and phase difference between a reference signal and a feedback signal; a digital phase difference counter coupled to the digital PFD for sampling the detection signal according to an oscillator signal to thereby generate a count value; a digital filter coupled to the digital phase difference counter for generating a control signal according to the count value; a digital controlled oscillator (DCO) coupled to the digital filter for generating the oscillator signal according to the control signal; and a frequency divider coupled to the DCO and the digital PFD for generating the feedback signal by dividing the oscillator signal.
Claims14
An all-digital phase-locked loop (ADPLL) comprising:
- a digital phase frequency detector (PFD) for detecting frequency difference and phase difference between a reference signal and a feedback signal to thereby generate a detection signal;
- a digital phase difference counter coupled to the digital phase frequency detector for sampling the detection signal according to an oscillator signal to thereby generate a count value;
- a digital filter coupled to the digital phase difference counter for generating a control signal according to the count value, comprising:
- a delay unit for delaying the count value to generate a delayed count value;
- a calculating unit for calculating the count value and the delayed count value to generate a calculated value;
- and
- an encoder coupled to the calculating unit for generating the control signal according to the calculated value;
- a digital controlled oscillator (DCO) coupled to the digital filter for generating the oscillator signal according to the control signal;
- and
- a frequency divider coupled to the digital controlled oscillator and the digital phase frequency detector for generating the feedback signal by dividing the oscillator signal.
A digital phase-locked loop (DPLL) comprising:
- a phase frequency detector (PFD) for detecting a reference signal and a feedback signal to generate a detection signal;
- an difference estimator coupled to the phase frequency detector for sampling the detection signal and generating an estimation signal according to an oscillator signal;
- a digital filter coupled to the difference estimator for generating a control signal according to the estimation signal, comprising:
- a delay unit for delaying the estimation signal to generate a delayed estimation signal;
- a calculating unit for calculating the estimation signal and the delayed estimation signal to generate a calculated value;
- and
- an encoder coupled to the calculating unit for generating the control signal according to the calculated value;
- and
- a digital controlled oscillator (DCO) coupled to the digital filter for generating the oscillator according to the control signal;
- wherein the feedback signal corresponds to the oscillator signal.
Dependencies are inferred from the claim text.