Differential input receiver having over-voltage protection

A differential receiver circuit comprising:

• a first input transistor and a second input transistor, wherein a drain terminal of the first input transistor is coupled to a first bias node and a drain terminal of the second input transistor is coupled to a second bias node;
• a first bias transistor having a source terminal coupled to the first bias node;
• a second bias transistor having a source terminal coupled to the second bias node;
• a first current source coupled to provide current to the first bias node;
• and
• a second current source coupled to provide current to the second bias node;
• wherein the differential receiver circuit is coupled to a voltage node and a reference node and wherein each of the first and second current sources are configured to provide current to the first and second bias nodes respectively such that the voltage on each of the first and second bias node remains within approximately a threshold voltage amount of one half a voltage present on the voltage node.

A circuit comprising:

• an input transistor, wherein a first terminal of the input transistor is coupled to a first bias node;
• a first bias transistor, wherein a first terminal of the bias transistor is coupled to the first bias node;
• and
• a current source coupled to provide current to the first bias node;
• wherein the circuit is coupled to a first voltage node and a second voltage node, wherein the current source is configured to provide current to the bias node such that the voltage present on the bias node remains within approximately a threshold voltage of a midpoint between a voltage present on the first voltage node and a voltage present on the second voltage node.