Voltage controlled delay line (VCDL) having embedded multiplexer and interpolation functions

A delay locked loop (DLL) comprising:

• a phase detector configured to receive a reference clock signal;
• a filter coupled to receive an output from the phase detector;
• a counter coupled to receive an output from the filter;
• a digital-to-analog converter (DAC) coupled to receive an output from the counter;
• and
• a voltage controlled delay line (VCDL) coupled to receive a control voltage from the DAC and the reference clock signal, wherein the VCDL includes a plurality of cells, wherein each of the plurality of cells includes two or more inputs and an output, and wherein each of the plurality of cells is configured to provide a delay, and is further configured to operate in one of a first mode providing an interpolation function or a second mode providing a multiplexer function;
• wherein, when providing the multiplexer function, one of the two or more inputs is selected such that it is operatively coupled to the output;
• wherein, when providing in the interpolation function, two of the two or more inputs are selected such that each of the selected two inputs is operatively coupled to the output;
• wherein the VCDL further includes two or more selection circuits, wherein each of the two or more selection circuits is associated with a corresponding one of the two or more inputs, and wherein each selection circuit is configured to, when enabled, operatively couples its corresponding input to the output.

A cell circuit configured for use in a voltage controlled delay line, the cell circuit comprising:

• two or more input nodes;
• and
• an output node;
• wherein the cell circuit is configured to provide a delay to signals provided to each of the two or more input nodes;
• wherein the cell circuit is configured to function as a multiplexer in a first mode of operation by selecting one of the two or more input nodes to be operatively coupled to the output node, wherein a signal conveyed on the output node in the first mode is a delayed version of a signal conveyed on the selected one of the two or more input nodes;
• and
• wherein the cell circuit is configured to function as an interpolator in a second mode of operation by selecting two of the two or more input nodes to be operatively coupled to the output node, wherein in the signal conveyed on the output node in the second mode is a delayed interpolation between input signals provided to the selected two input nodes.