Elastic pipeline latch with a safe mode

A latch circuit for receiving a data input signal and for providing an output signal, the latch circuit comprising:

• a buffer input for configuring the latch into a repeater state or a latch state;
• a plurality of drive transistors responsive to the buffer input and for driving the input signal through as the output signal;
• a pulse width/inhibit circuit coupled to the drive transistors;
• a reset threshold circuit coupled to the drive transistors for inhibiting oscillation of the drive transistors;
• and
• a latch circuit for passing a present state of the input signal to the output signal when configured as the repeater state and for maintaining a previous state of the output signal during transitions of a clock signal when configured as the latch state.

A digital integrated circuit having a configuring a signal path, comprising:

• a first logic module configured to transmit an output;
• a second logic module configured to receive the output;
• a configurable signal path for conveying the output from the first logic module to the second logic module, wherein the configurable signal path is variable by selectively including at least one latch, comprising:
• a control input for configuring the latch into a repeater state or a latch state;
• a drive component responsive to the control input and for driving an input signal through as an output signal;
• a pulse width/inhibit component coupled to the drive component;
• a reset threshold component coupled to the drive component for inhibiting oscillation of the drive component;
• and
• a latch component for passing a present state of the input signal to the output signal when configured as the repeater state and for maintaining a previous state of the output signal during transitions of a clock signal when configured as the latch state.