Systems for implementing high speed and high integration chips

Abstract

Disclosed are methods and systems for implementing various circuitry within a high speed, high frequency signal environment such as an integrated circuit. In one embodiment, an improved clock tree mechanism utilizes multiple low power drivers to distribute a clock signal to various load cells. In another embodiment, a single circuitry in current mode logic is used to implement a combined multiplexer, buffer and level shifter. In other embodiments, improved static and partially static flip-flop circuitry is disclosed which uses fewer devices and less power than conventional circuitry while achieving the same functionality.

Dependencies are inferred from the claim text.