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US 7,256,628 B2Granted
Speed-matching control method and circuit
AssigneeSun Microsystems, Inc.
InventorsRobert J. Drost, William S. Coates, Josephus C. Ebergen
Life of this patent
Estimating the term…
Abstract
One embodiment of the present invention provides a system that matches speeds of asynchronous operation between a local chip and a neighboring chip. The system derives an internal frequency signal from an internal oscillator on the local chip, and receives an external frequency signal from a neighboring chip. The system then compares the internal frequency signal with the external frequency signal to generate a control signal, which is applied to the local chip to adjust the operating speed of the local chip, and applied to the internal oscillator to adjust the frequency of the internal oscillator.
Claims24
A method for matching speeds of asynchronous operation between a local chip and a neighboring chip, the method comprising:
- deriving an internal frequency signal from an internal oscillator on the local chip;
- receiving an external frequency signal from a neighboring chip;
- comparing the internal frequency signal with the external frequency signal to generate a control signal;
- and
- adjusting the operating speed of the local chip by applying the control signal to the internal oscillator;
- wherein if the internal frequency signal is faster than the external frequency signal, the control signal causes the internal frequency signal to slow down;
- wherein the neighboring chip similarly adjusts the external frequency signal with respect to the internal frequency signal so that the local chip and the neighboring chip operate at a substantially maximum common frequency;
- wherein the local chip and the neighboring chip are coupled together in an asynchronous control loop, which determines the substantially maximum common frequency without reference to an external synchronous clock signal;
- wherein comparing the internal frequency signal with the external frequency signal involves applying the internal frequency signal to a first edge detector circuit which is used to gate a first current source;
- wherein comparing the internal frequency signal with the external frequency signal involves applying the external frequency signal to a second edge detector circuit which is used to gate a second current source;
- and
- wherein an integrating capacitor and an offset current source are used to ensure that the frequency signal with the higher maximum frequency will operate at just above the maximum frequency of the frequency signal with the lower maximum frequency.
9 more elements
An apparatus for matching speeds of asynchronous operation between a local chip and a neighboring chip, the apparatus comprising:
- an internal oscillator on the local chip, from which an internal frequency signal can be derived;
- a receiving mechanism configured to receive an external frequency signal from a neighboring chip;
- a comparison mechanism configured to compare the internal frequency signal with the external frequency signal to generate a control signal;
- and
- an adjusting mechanism configured to adjust the operating speed of the local chip and the internal oscillator by applying the control signal to the internal oscillator;
- wherein if the internal frequency signal is faster than the external frequency signal, the control signal causes the internal frequency signal to slow down;
- wherein the neighboring chip similarly adjusts the external frequency signal with respect to the internal frequency signal so that the local chip and the neighboring chip operate at a substantially maximum common frequency;
- and
- wherein the local chip and the neighboring chip are coupled together in an asynchronous control loop, which determines the substantially maximum common frequency without reference to an external synchronous clock signal;
- wherein comparing the internal frequency signal with the external frequency signal involves applying the internal frequency signal to a first edge detector circuit which is used to gate a first current source;
- wherein comparing the internal frequency signal with the external frequency signal involves applying the external frequency signal to a second edge detector circuit which is used to gate a second current source;
- and
- wherein an integrating capacitor and an offset current source are used to ensure that the frequency signal with the higher maximum frequency will operate at just above the maximum frequency of the frequency signal with the lower maximum frequency.
10 more elements
A computer system that includes a circuit for matching speeds of asynchronous operation between a local chip and a neighboring chip, the circuit comprising:
- a central processing unit;
- a semiconductor memory;
- an internal oscillator circuit on the local chip, from which an internal frequency signal can be derived;
- a receiver circuit for receiving an external frequency signal from a neighboring chip;
- a comparison circuit for comparing the internal frequency signal with the external frequency signal to generate a control signal;
- and
- an adjustment circuit for adjusting the operating speed of the local chip and the internal oscillator by applying the control signal to and the internal oscillator;
- wherein if the internal frequency signal is faster than the external frequency signal, the control signal causes the internal frequency signal to slow down;
- wherein the neighboring chip similarly adjusts the external frequency signal with respect to the internal frequency signal so that the local chip and the neighboring chip operate at a substantially maximum common frequency;
- and
- wherein the local chip and the neighboring chip are coupled together in an asynchronous control loop, which determines the substantially maximum common frequency without reference to an external synchronous clock signal;
- wherein comparing the internal frequency signal with the external frequency signal involves applying the internal frequency signal to a first edge detector circuit which is used to gate a first current source;
- wherein comparing the internal frequency signal with the external frequency signal involves applying the external frequency signal to a second edge detector circuit which is used to gate a second current source;
- and
- wherein an integrating capacitor and an offset current source are used to ensure that the frequency signal with the higher maximum frequency will operate at just above the maximum frequency of the frequency signal with the lower maximum frequency.
12 more elements
Dependencies are inferred from the claim text.