Alignment of local transmit clock to synchronous data transfer clock having programmable transfer rate

A method in an integrated circuit, the method comprising:

• receiving a received reference clock of a synchronous communications system at a pad of the integrated circuit, the pad providing a contact interface for the integrated circuit with a trace configured for supplying the received referenced clock;
• outputting, by a phase selection circuit in the integrated circuit, a phase-adjusted local clock in response to a local clock signal and a phase selection value, the phase selection circuit configured for outputting the local clock signal as the phase-adjusted local clock and having a selected phase based on the phase selection value, the outputting including aligning the phase-adjusted local clock toward the received reference clock based on the phase selection value;
• digitally sampling the received reference clock, by a synchronizer in the integrated circuit, relative to the phase-adjusted local clock, and outputting by the synchronizer a digital phase bit identifying whether the phase-adjusted local clock has a later phase relative to the received reference clock;
• selectively performing one of incrementing or decrementing of a counted value by a counter based on the digital phase bit, the counted value having a first prescribed number of bits;
• and
• outputting from the counter to the phase selection circuit a prescribed number of most significant bits from the counted value as the phase selection value, the prescribed number of most significant bits from the counted value less than the first prescribed number of bits, wherein the phase selection value specifies one of a plurality of available digital phase increments across a period of a single clock cycle.