US 7,256,626 B2Granted

Low-voltage differential signal driver with pre-emphasis circuit

AssigneeUnited Microelectronics Corp.

InventorsHai Thanh Nguyen, Chung-Cheng Tsai

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Abstract

A low-voltage differential signal driver with a pre-emphasis circuit having a current control circuit and a pre-emphasis circuit is provided. Wherein, the pre-emphasis circuit includes the current sourcing circuit and the current sinking circuit, both of which have similar circuit structure, coupled to the current control circuit, respectively. The current sourcing circuit and the current sinking circuit are controlled by two sets of driving signals, so that the pre-emphasis circuit provides an extra driving current to the current control circuit at an instant when the current control circuit switches the current direction. In addition, each set of driving signals contains two synchronous but phase-inversed driving signals. The time it takes for the current steering circuit to switch terminated resistor current between upward and downward directions is decreased.

Claims20

Dependent claims

A pre-emphasis circuit suitable for a low-voltage differential signal (LVDS) driver with a current input end and a current output end, the pre-emphasis circuit comprising:

a first PMOS transistor, wherein the first source/drain end thereof is coupled to a voltage supply through a first resistor and the gate end thereof receives a first driving signal with a preset time delay;
a second PMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first PMOS transistor, the gate end thereof receives a second driving signal, and the second source/drain end is coupled to said current input end;
a third PMOS transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first PMOS transistor and the gate end thereof receives said second driving signal with said preset time delay;
a fourth PMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third PMOS transistor, the gate end thereof receives said first driving signal, and the second source/drain end thereof is coupled to the second source/drain end of said second PMOS transistor;
a first NMOS transistor, wherein the first source/drain end thereof is coupled to said current output end and the gate end receives a third driving signal;
a second NMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first NMOS transistor, the gate end thereof receives a fourth driving signal with said preset time delay, and the second source/drain end thereof is grounded through a second resistor;
a third NMOS transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first NMOS transistor and the gate end thereof receives said fourth driving signal;
and
a fourth NMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third NMOS transistor, the gate end thereof is coupled to said third driving signal with said preset time delay, and the second source/drain end thereof is coupled to the second source/drain end of said second NMOS transistor.

6 more elements

A pre-emphasis circuit suitable for a low-voltage differential signal (LVDS) driver with a current input end and a current output end, the pre emphasis circuit comprising:

a first transistor, wherein the first source/drain end thereof is coupled to a voltage supply through a first resistor and the gate end thereof receives a first driving signal with a preset time delay;
a second transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first transistor, the gate end thereof receives a second driving signal, and the second source/drain end thereof is coupled to said current input end;
a third transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first transistor and the gate end thereof receives said second driving signal with said preset time delay;
a fourth transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third transistor, the gate end thereof receives said first driving signal, and the second source/drain end thereof is coupled to the second source/drain end of said second transistor;
a fifth transistor, wherein the first source/drain end thereof is coupled to said current output end, and the gate end thereof receives a third driving signal;
a sixth transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said fifth transistor, the gate end thereof receives a fourth driving signal with said preset time delay, and the second source/drain end thereof is grounded through a second resistor;
a seventh transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said fifth transistor and the gate end thereof receives said fourth driving signal;
and
an eighth transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said seventh transistor, the gate end thereof is coupled to said third driving signal with said preset time delay, and the second source/drain end thereof is coupled to the second source/drain end of said sixth transistor.

6 more elements

A low-voltage differential signal (LVDS) driver with a pre-emphasis circuit, comprising:

a current control circuit having a current input end, a current output end, a first output end and a second output end, wherein said current input end is coupled to a voltage supply through a first driving current source, said current output end is grounded through a second driving current source, and said first output end and said second output end are coupled to a load;
a first PMOS transistor, wherein the first source/drain end thereof is coupled to said voltage supply through a first resistor, and the gate end thereof receives a first driving signal with a preset time delay;
a second PMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first PMOS transistor, the gate end thereof receives a second driving signal, and the second source/drain end thereof is coupled to said current input end;
a third PMOS transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first PMOS transistor, and the gate end thereof receives said second driving signal with said preset time delay;
a fourth PMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third PMOS transistor, the gate end thereof receives said first driving signal, and the second source/drain end thereof is coupled to the second source/drain end of said second PMOS transistor;
a first NMOS transistor, wherein the first source/drain end thereof is coupled to said current output end, and the gate end thereof receives a third driving signal;
a second NMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first NMOS transistor, the gate end thereof receives a fourth driving signal with said preset time delay, and the second source/drain end is grounded through a second resistor;
a third NMOS transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first NMOS transistor, and the gate end thereof receives said fourth driving signal;
and
a fourth NMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third NMOS transistor, the gate end thereof receives said third driving signal with said preset time delay, and the second source/drain end thereof is coupled to the second source/drain end of said second NMOS transistor.

7 more elements

A low-voltage differential signal (LVDS) driver with a pre-emphasis circuit, comprising:

a current control circuit having a current input end, a current output end, a first output end and a second output end, wherein said current input end is coupled to a voltage supply through a driving current source, said current output end is grounded through a first resistor, and said first output end and said second output end are coupled to a load;
a first PMOS transistor, wherein the first source/drain end thereof is coupled to said voltage supply through a second resistor and the gate end thereof receives a first driving signal with a preset time delay;
a second PMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first PMOS transistor, the gate end thereof receives a second driving signal, and the second source/drain end thereof is coupled to said current input end;
a third PMOS transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first PMOS transistor and the gate end thereof receives said second driving signal with said preset time delay;
a fourth PMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third PMOS transistor, the gate end thereof receives said first driving signal, and the second source/drain end thereof is coupled to the second source/drain end of said second PMOS transistor;
a first NMOS transistor, wherein the first source/drain end thereof is coupled to said current output end and the gate end thereof receives a third driving signal;
a second NMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first NMOS transistor, the gate end thereof receives a fourth driving signal with said preset time delay, and the second source/drain end thereof is grounded through a third resistor;
a third NMOS transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first NMOS transistor and the gate end thereof receives said fourth driving signal;
and
a fourth NMOS transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third NMOS transistor, the gate end thereof is coupled to said third driving signal with said preset time delay, and the second source/drain end thereof is coupled to the second source/drain end of said second NMOS transistor.

7 more elements

A low-voltage differential signal (LVDS) driver with a pre-emphasis circuit, comprising:

a current control circuit, comprising a current input end, a current output end, a first output end and a second output end, wherein said first output end and said second output end are coupled to a load;
a first transistor, wherein the first source/drain end thereof is coupled to a voltage supply through a first resistor and the gate end thereof receives a first driving signal with a preset time delay;
a second transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said first transistor, the gate end thereof receives a second driving signal, and the second source/drain end thereof is coupled to said current input end;
a third transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said first transistor and the gate end thereof receives said second driving signal with said preset time delay;
a fourth transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said third transistor, the gate end thereof receives said first driving signal, and the second source/drain end thereof is coupled to the second source/drain end of said second transistor;
a fifth transistor, wherein the first source/drain end thereof is coupled to said current output end and the gate end thereof receives a third driving signal;
a sixth transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said fifth transistor, the gate end thereof receives a fourth driving signal with said preset time delay, and the second source/drain end thereof is grounded through a second resistor;
a seventh transistor, wherein the first source/drain end thereof is coupled to the first source/drain end of said fifth transistor and the gate end thereof receives said fourth driving signal;
and
an eighth transistor, wherein the first source/drain end thereof is coupled to the second source/drain end of said seventh transistor, the gate end thereof is coupled to said third driving signal with said preset time delay, and the second source/drain end thereof is coupled to the second source/drain end of said sixth transistor.

7 more elements

Dependencies are inferred from the claim text.