US 7,256,622 B2 · AND, OR, NAND, and NOR logical gates

Abstract

A logic family consisting of four basic logical circuits performing AND, OR, NAND and NOR functions is disclosed. The AND and OR logic circuits function without a power supply and complementary input signals. The NAND and NOR logic circuits function without complementary input signals. The AND and OR logic circuits are constructed using two MOS (Metal Oxide Semiconductor) transistors, namely, one P-channel MOS transistor and one N-channel MOS transistor. The NAND and NOR logic circuits are constructed using four MOS transistors, namely, two P-channel MOS transistors and two N-channel MOS transistors. The logic circuits may have higher speed, occupy less area and consume less power because power supply is not needed, complementary input signals are not used and fewer transistors are used. The logic circuits may have increased performance relative to CMOS (Complementary MOS) logic circuits, CPL (Complementary Pass Logic) circuits and DPL (Dual Pass Logic) circuits.

Claims18

Dependent claims

A logic circuit having an output for performing logical operations without a power supply and without complementary input signals, comprising:

(a) a first type MOS transistor having a source, a drain and a gate, the source of the said first MOS transistor is coupled to a first input terminal, the source of the said first MOS transistor is also coupled to the gate of the said first MOS transistor, the gate of the said first MOS transistor is coupled to a gate of a second type MOS transistor, the drain of the said first MOS transistor is coupled to the output of the logic circuit and
(b) a second type MOS transistor having a source, a drain and a gate, the source of the said second MOS transistor is coupled to a second input terminal, the gate of the said second MOS transistor is coupled to the gate of the said first MOS transistor, the drain of the said second MOS transistor is coupled to the output of the logic circuit.
whereby logical operation of the two input signals applied to the said first and said second input terminals is performed.

A logic circuit having an output for performing logical operations without complementary input signals, comprising:

(a) a first type MOS transistor having a source, a drain and a gate, the source of the said first MOS transistor is coupled to a first input terminal, the source of the said first MOS transistor is also coupled to the gate of the said first MOS transistor, the gate of the said first MOS transistor is coupled to a gate of a second type MOS transistor, the drain of the said first MOS transistor is coupled to a gate of a third MOS transistor and
(b) a second type MOS transistor having a source, a drain and a gate, the source of the said second MOS transistor is coupled to a second input terminal, the gate of the said second MOS transistor is coupled to the gate of the said first MOS transistor, a gate of a said second MOS transistor is coupled to the drain of the fourth MOS transistor and
(c) a third type MOS transistor having a source, a drain and a gate, the source of the said third MOS transistor is coupled to a power supply, the gate of the said third MOS transistor is coupled to the drain of the said first MOS transistor, the drain of the said third MOS transistor is coupled to the output of the logic circuit and
(d) a fourth type MOS transistor having a source, a drain and a gate, the source of the said fourth MOS transistor is coupled to the ground terminal, the gate of the said fourth MOS transistor is coupled to the drain of the said second MOS transistor, the drain of the said fourth MOS transistor is coupled to the output of the logic circuit.
whereby logical operation of the two input signals applied to the said first and said second input terminals is performed.

2 more elements

A logic circuit having an output for performing logical operations without complementary input signals, comprising:

(a) a first type MOS transistor having a source, a drain and a gate, the source of the said first MOS transistor is coupled to a first input terminal, the gate of the said first MOS transistor is coupled to a gate of a second type MOS transistor, the drain of the said first MOS transistor is coupled to a gate of a third MOS transistor and
(b) a second type MOS transistor having a source, a drain and a gate, the source of the said second MOS transistor is coupled to a second input terminal, the source of the said second MOS transistor is also coupled to the gate of the said second MOS transistor, the gate of the said second MOS transistor is coupled to the gate of the first MOS transistor, the drain of the said second MOS transistor is coupled to a gate of a fourth MOS transistor and
(c) a third type MOS transistor having a source, a drain and a gate, the source of the said third MOS transistor is coupled to a power supply, the gate of the said third MOS transistor is coupled to the drain of the said first MOS transistor, the drain of the said third MOS transistor is coupled to the output of the logic circuit and
(d) a fourth type MOS transistor having a source, a drain and a gate, the source of the said fourth MOS transistor is coupled to the ground terminal, the gate of the said fourth MOS transistor is coupled to the drain of the said second MOS transistor, the drain of the said fourth MOS transistor is coupled to the output of the logic circuit.
whereby logical operation of the two input signals applied to the said first and said second input terminals is performed.

2 more elements

Dependencies are inferred from the claim text.

AND, OR, NAND, and NOR logical gates

Life of this patent

AND, OR, NAND, and NOR logical gates

Life of this patent

Abstract

Claims18