# US 7,256,621 B2 · Keeper circuits having dynamic leakage compensation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 7,256,621 B2 - Document ID: US7256621B2 - Status: Granted - Kind: B2 - Application number: 11/089,956 - Filed: 2005-03-25 - Published: 2006-09-28 - Granted: 2007-08-14 - Earliest claimed: 2005-03-25 - Assignees: Fujitsu Limited - Inventors: Yolin Lih; William W. Walker - Web page: https://patentgrep.com/patent/US7256621B2 ## CPC - H03K 19/0013: {in field effect transistor circuits} - H03K 19/0963: {using transistors of complementary type (H03K19/0966 takes precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Disclosed are keeper circuits for electronic circuits that selectively maintain the voltage level of an intermediate circuit node at a desired level. In one exemplary embodiment, a keeper transistor either provides current or drains current from the intermediate node to maintain the desired voltage level in response to a signal to do so. The keeper circuit works against a leakage current that either drains current from the node or supplies current to the node. A current-setting transistor is coupled in series with the keeper transistor to set the maximum current through the keeper circuit to a value that is related to this leakage current, preferably tracking the leakage current. With this construction, the current-setting transistor is able to track variations in the leakage current caused by variations in the manufacturing process, and thereby provide dynamic leakage compensation. ## Claims ### Claim 1 A keeper circuit for use in a circuit powered by a voltage provided between a first supply line and a second supply line, the keeper circuit for selectively maintaining an intermediate node of the circuit at a first voltage level in opposition to a leakage current being conducted between the intermediate node and the second supply line, the keeper circuit comprising: a keeper transistor having a first conduction terminal, a second conduction terminal, and a modulation terminal, the modulation terminal receiving a signal indicating whether the keeper transistor is to maintain an intermediate node at a first voltage level; a first transistor of a first conductivity type having a first conduction terminal, a second conduction terminal, and a modulation terminal, one of the conduction terminals of the first transistor being coupled to a conduction terminal of the keeper transistor to provide a series circuit of the transistors, the series circuit being coupled between the intermediate node and the first supply line; a second transistor of the first conductivity type having a first conduction terminal, a second conduction terminal, and a modulation terminal, the second transistor being coupled to the first transistor in a current-mirror relationship such that the maximum amount of current conducted by the first transistor through its conduction terminals is related to the current conducted by the second transistor through its conduction terminals; and a sensing network having a first conduction terminal coupled to the first conduction terminal of the second transistor and a second conduction terminal coupled to a source of potential, the sensing network comprising at least one transistor of a second conductivity type opposite to the first conductivity type and generating a current at its first conduction terminal that is in relation to the leakage current being conducted between the intermediate node and the second supply line. ### Claim 2 (depends on 1) The keeper circuit of claim 1 wherein the keeper transistor is coupled to the intermediate node and the first transistor is coupled to the first supply line. ### Claim 3 (depends on 1) The keeper circuit of claim 1 wherein the first transistor is coupled to the intermediate node and the keeper transistor is coupled to the first supply line. ### Claim 4 (depends on 1) The keeper circuit of claim 1 wherein the modulation terminal of the keeper transistor receives a signal related to the voltage state of the intermediate node. ### Claim 5 (depends on 1) The keeper circuit of claim 1 wherein the keeper transistor has a W/L ratio that is larger than the W/L ratio of the first transistor. ### Claim 6 (depends on 1) The keeper circuit of claim 1 wherein the modulation terminal and the second conduction terminal of the second transistor are coupled together, and wherein the modulation terminal of the second transistor is coupled to the modulation terminal of the first transistor, and wherein the second conduction terminal of the second transistor is coupled to the second conduction terminal of the first transistor. ### Claim 7 (depends on 1) The keeper circuit of claim 1 wherein the sensing network comprises a PMOS transistor, and wherein each of the first and second transistors comprises a respective NMOS transistor. ### Claim 8 (depends on 1) The keeper circuit of claim 1 wherein the sensing network comprises an NMOS transistor, and wherein each of the first and second transistors comprises a respective PMOS transistor. ### Claim 9 (depends on 1) The keeper circuit of claim 1 wherein the at least one transistor of the sensing network has a first conduction terminal, a second conduction terminal, and a modulation terminal, wherein the modulation terminal and second conduction terminal are coupled together, and wherein the first conduction terminal is coupled to the first conduction terminal of the second transistor. ### Claim 10 (depends on 1) The keeper circuit of claim 1 wherein the at least one transistor of the sensing network has a first conduction terminal, a second conduction terminal, and a modulation terminal, wherein the modulation terminal and second conduction terminal are coupled to the second supply line, and wherein the first conduction terminal is coupled to the first conduction terminal of the second transistor. ### Claim 11 (depends on 1) The keeper circuit of claim 1 wherein a plurality of N legs of a logic circuit are coupled to the intermediate node, each leg having at least one transistor; wherein the keeper circuit and the legs of the logic circuit are disposed on a common substrate. ### Claim 12 (depends on 11) The keeper circuit of claim 11 wherein the sensing network and at least one of the transistors of the logic circuit are disposed in a common substrate well. ### Claim 13 (depends on 1) The keeper circuit of claim 1 wherein a plurality of N legs of a logic circuit are coupled to the intermediate node, each leg having at least one transistor; wherein the keeper circuit and the legs of the logic circuit are disposed on a common substrate that has transistors of the second conductivity type integrated thereon, with a first group of such transistors having a first construction to provide a low range of threshold voltages and a second group of such transistors having a second construction to provide a high range of threshold voltages; and wherein at least one transistor of the logic circuit comprises a transistor having the first construction. ### Claim 14 (depends on 1) The keeper circuit of claim 1 wherein a plurality of legs of a logic circuit are coupled to the intermediate node, each such leg comprising one or more serially-connected elements, each such element comprising a single transistor or a group of parallel-connected transistors; wherein each leg has an expected maximum leakage current equal to the expected leakage current of the element of the leg having the largest collective amount of transistor gate width; wherein the logic circuit has an expected maximum leakage current equal to the sum of the expected maximum leakage currents of the legs; and wherein the maximum current of the first transistor is between 1.1 times and 10 times the expected maximum leakage current of the logic circuit. ### Claim 15 (depends on 14) The keeper circuit of claim 14 wherein the maximum current of the first transistor is between 2 times and 6 times the expected maximum leakage current of the logic circuit. ### Claim 16 A keeper circuit for use in a digital circuit powered by a voltage provided between a first supply line and a second supply line, the keeper circuit for selectively maintaining an intermediate node of the digital circuit at a first voltage level, the keeper circuit comprising: a keeper transistor having a first conduction terminal, a second conduction terminal, and a modulation terminal, the modulation terminal receiving a signal indicating whether the keeper transistor is to maintain an intermediate node at a first voltage level; a first PMOS transistor having a drain terminal, a source terminal, and a gate terminal, one of the source and drain terminals of the first PMOS transistor being coupled to a conduction terminal of the keeper transistor to provide a series circuit of the transistors, the series circuit being coupled between the intermediate node and the first supply line; a second PMOS transistor having a drain terminal, a source terminal, and a gate terminal, the second PMOS transistor being coupled to the first PMOS transistor in a current-mirror relationship such that the maximum amount of current conducted by the first PMOS transistor through its drain and source terminals is related to the current conducted by the second PMOS transistor through its source and drain terminals; and at least a first NMOS transistor having a drain terminal coupled to the drain terminal of the second PMOS transistor, a source terminal, and a gate terminal, wherein the gate terminal and the source terminal are coupled together and to a source of potential. ### Claim 17 (depends on 16) The keeper circuit of claim 16 wherein the keeper transistor is coupled to the intermediate node and the first PMOS transistor is coupled to the first supply line. ### Claim 18 (depends on 16) The keeper circuit of claim 16 wherein the first PMOS transistor is coupled to the intermediate node and the keeper transistor is coupled to the first supply line. ### Claim 19 (depends on 16) The keeper circuit of claim 16 wherein the modulation terminal of the keeper transistor receives a signal related to the voltage state of the intermediate node. ### Claim 20 (depends on 16) The keeper circuit of claim 16 wherein the keeper transistor has a W/L ratio that is larger than the W/L ratio of the first PMOS transistor. ### Claim 21 (depends on 16) The keeper circuit of claim 16 wherein the gate terminal and the drain terminal of the second PMOS transistor are coupled together, and wherein the gate terminal of the second PMOS transistor is coupled to the gate terminal of the first PMOS transistor, and wherein the source terminal of the second PMOS transistor is coupled to the source terminal of the first PMOS transistor. ### Claim 22 (depends on 16) The keeper circuit of claim 16 wherein the gate and source terminals of the at least first NMOS transistor are coupled to the second supply line. ### Claim 23 (depends on 16) The keeper circuit of claim 16 wherein a plurality of N legs of a logic circuit are coupled to the intermediate node, each leg having at least one transistor; wherein the keeper circuit and the legs of the logic circuit are disposed on a common substrate. ### Claim 24 (depends on 16) The keeper circuit of claim 16 wherein a plurality of N legs of a logic circuit are coupled to the intermediate node, each leg having at least one transistor; wherein the keeper circuit and the legs of the logic circuit are disposed on a common substrate that has NMOS transistors integrated thereon, with a first group of such NMOS transistors having a first construction to provide a low range of threshold voltages and a second group of such NMOS transistors having a second construction to provide a high range of threshold voltages; and wherein at least one transistor of the logic circuit comprises an NMOS transistor having the first construction. ### Claim 25 (depends on 16) The keeper circuit of claim 16 wherein a plurality of legs of a logic circuit are coupled to the intermediate node, each such leg comprising one or more serially-connected elements, each such element comprising a single transistor or a group of parallel-connected transistors; wherein each leg has an expected maximum leakage current equal to the expected leakage current of the element of the leg having the largest collective amount of transistor gate width; wherein the logic circuit has an expected maximum leakage current equal to the sum of the expected maximum leakage currents of the legs; and wherein the maximum current of the first PMOS transistor is between 1.1 times and 10 times the expected maximum leakage current of the logic circuit. ### Claim 26 (depends on 25) The keeper circuit of claim 25 wherein the maximum current of the first PMOS transistor is between 2 times and 6 times the expected maximum leakage current of the logic circuit. ### Claim 27 A keeper circuit for use in a circuit powered by a voltage provided between a first supply line and a second supply line, the keeper circuit for selectively maintaining an intermediate node of the circuit at a first voltage level in opposition to a leakage current being conducted between the intermediate node and the second supply line, the keeper circuit comprising: a keeper transistor having a first conduction terminal, a second conduction terminal, and a modulation terminal, the modulation terminal receiving a signal indicating whether the keeper transistor is to maintain an intermediate node at a first voltage level; characterized by a current-setting transistor having a first conduction terminal, a second conduction terminal, and a modulation terminal, the current-setting transistor being configured to set the maximum current flow between its first and second conduction terminals in relation to the leakage current being conducted between the intermediate node and the second supply line; and characterized in that a conduction terminal of the keeper transistor is coupled to a conduction terminal of the current-setting transistor to provide a series circuit of the transistors, and in that the series circuit is coupled between the intermediate node and the first supply line. ### Claim 28 (depends on 27) The keeper circuit of claim 27 further characterized in that the current-setting transistor comprises a transistor of a first conductivity type, and further characterized by: a mirror transistor of the first conductivity type having a first conduction terminal, a second conduction terminal, and a modulation terminal, the mirror transistor being coupled to the current-setting transistor in a current-mirror relationship such that the maximum amount of current conducted by the current-setting transistor through its conduction terminals is related to the current conducted by the mirror transistor through its conduction terminals; and a sensing network having one or more transistors of a second conductivity type opposite to the first conductivity type, each such transistor having a first conduction terminal coupled to the first conduction terminal of the mirror transistor, a second conduction terminal, and a modulation terminal, the modulation and second conduction terminals of the one or more transistors of the sensing network being configured with at least one source of potential to generate a collective leakage current that is in relation to the leakage current being conducted between the intermediate node and at least one of the supply lines. ### Claim 29 (depends on 28) The keeper circuit of claim 28 wherein the current-setting transistor is of the first conductivity type, wherein the modulation terminal and the second conduction terminal of the mirror transistor are coupled together, and wherein the modulation terminal of the mirror transistor is coupled to the modulation terminal of the current-setting transistor, and wherein the second conduction terminal of the mirror transistor is coupled to the second conduction terminal of the current-setting transistor. ### Claim 30 (depends on 27) The keeper circuit of claim 27 wherein a plurality of N legs of a logic circuit are coupled to the intermediate node, each leg having at least one transistor; wherein the keeper circuit and the legs of the logic circuit are disposed on a common substrate that has transistors of a conductivity type integrated thereon with a first group of such transistors having a first construction to provide a low range of threshold voltages and a second group of such transistors having a second construction to provide a high range of threshold voltages; and wherein at least one transistor of the logic circuit comprises a transistor having the first construction. ### Claim 31 (depends on 27) The keeper circuit of claim 27 wherein a plurality of legs of a logic circuit are coupled to the intermediate node, each such leg comprising one or more serially-connected elements, each such element comprising a single transistor or a group of parallel-connected transistors; wherein each leg has an expected maximum leakage current equal to the expected leakage current of the element of the leg having the largest collective amount of transistor gate width; wherein the logic circuit has an expected maximum leakage current equal to the sum of the expected maximum leakage currents of the legs; and wherein the maximum current of the current-setting transistor is between 1.1 times and 10 times the expected maximum leakage current of the logic circuit. ### Claim 32 (depends on 31) The keeper circuit of claim 31 wherein the maximum current of the current-setting transistor is between 2 times and 6 times the expected maximum leakage current of the logic circuit. ### Claim 33 (depends on 27) The keeper circuit of claim 27 wherein each of the keeper transistor and the current-setting transistor has a conductance between its first and second conduction terminals, and wherein the conductance of the keeper transistor is greater than the conductance of the current-setting transistor. ### Claim 34 (depends on 27) The keeper circuit of claim 27 wherein the modulation terminal of the keeper transistor is driven by the output of an inverter. ### Claim 35 (depends on 27) The keeper circuit of claim 27 wherein the modulation terminal of the current-setting transistor is coupled to a circuit node that is different from the circuit nodes coupled to conduction terminals of the current-setting transistor. ### Claim 36 (depends on 27) The keeper circuit of claim 27 wherein the keeper transistor has a W/L ratio that is larger than the W/L ratio of the current-setting transistor. ### Claim 37 A keeper circuit for use in a circuit powered by a voltage provided between a first supply line and a second supply line, the keeper circuit for selectively maintaining an intermediate node of the circuit at a first voltage level in opposition to a leakage current being conducted between the intermediate node and the second supply line, the keeper circuit comprising: a keeper transistor having a first conduction terminal, a second conduction terminal, and a modulation terminal, the modulation terminal receiving a signal indicating whether the keeper transistor is to maintain an intermediate node at a first voltage level; a sensing network having one or more transistors configured to generate a leakage current that is in relation to the leakage current being conducted between the intermediate node and at least one of the supply lines; and a current-setting transistor having a first conduction terminal, a second conduction terminal, and a modulation terminal, the current-setting transistor being configured to set the maximum current flow between its first and second conduction terminals in relation to the leakage current generated by the sensing network; and wherein a conduction terminal of the keeper transistor is coupled to a conduction terminal of the current-setting transistor to provide a series circuit of the transistors, and wherein the series circuit is coupled between the intermediate node and the first supply line.