Programmable interconnect architecture for programmable logic devices

A programmable logic device, comprising:

• a programmable logic block having a set of inputs organized into input groups;
• a horizontal routing resource;
• a vertical routing resource, wherein the vertical routing resource and horizontal routing resource each includes a plurality of wires organized into wire groups;
• and
• a switch matrix configured to couple a wire group to an input group, wherein a given wire group in the horizontal routing resource is couplable to a given input group independently of whether another wire group in the vertical routing resource is also couplable to the given input group.

A programmable logic device, comprising:

• a plurality of vertical routing resources;
• a plurality of horizontal routing resources, wherein at least a first one of the horizontal routing resources and at least a first one of the vertical routing resources both include a plurality of wires organized into at least a first wire group and a second wire group;
• a first input switch matrix operable to select signals from the first wire group in the first horizontal routing resource and from the first wire group in the first vertical routing resources to provide an input signal to a first lookup table (LUT) input;
• and
• a second input switch matrix operable to select signals from the first wire group in the first horizontal routing resource and from the second wire group in the first vertical routing resource to provide an input signal to a second LUT input.