Method and apparatus for reducing leakage in integrated circuits
AssigneeUniversity of South Florida
InventorsNagarajan Ranganathan, Narender Hanchate
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Abstract
An efficient design methodology in accordance with the present invention is described for reducing the leakage power in CMOS circuits. The method and apparatus in accordance with the present invention yields better leakage reduction as the threshold voltage decreases and hence aids in further reduction of supply voltage and minimization of transistor sizes. Unlike other leakage control techniques, the technique of the present invention does not need any control circuitry to monitor the states of the circuit. Hence, avoiding the sacrifice of obtained leakage power reduction in the form of dynamic power consumed by the additional circuitry to control the overall circuit states.
Claims25
An apparatus comprising:
- a leakage reduction circuit to be coupled to an integrated logic circuit, the integrated logic circuit comprising a plurality of logic gates, the leakage reduction circuit comprising a p-type leakage control transistor and an n-type leakage control transistor arranged such that an input to the integrated logic circuit will place one of either the p-type leakage control transistor or the n-type leakage control transistor near it's associated cut-off voltage.
A leakage power reduction method for use with integrated circuits, the method comprising the steps of:
- identifying an integrated logic circuit, the integrated logic circuit comprising a plurality of logic gates;
- inserting a leakage reduction circuit comprising a p-type leakage control transistor and an n-type leakage control transistor arranged such that an input to the integrated logic circuit will place one of either the p-type leakage control transistor or the n-type leakage control transistor near it's associated cut-off voltage.
A method of obtaining a leakage controlled complementary metal oxide semiconductor circuit, comprising the steps of:
- identifying a gate-level netlist of a complementary metal oxide semiconductor logic circuit;
- inputting the netlist to a script to generate a textual description of the logic circuit;
- performing mapping of the textual description to generate a plurality of static complex complementary metal oxide semiconductor gates having a common pull-up node and a common pull-down node;
- introducing a leakage reduction circuit coupled between the pull-up node and the pull-down node of the static complex complementary metal oxide semiconductor, the leakage reduction circuit having one p-type transistor and one n-type transistor.
Dependencies are inferred from the claim text.