Memory expansion and chip scale stacking system and method

A memory access system comprising:

• a high-density circuit module comprising:
• a first CSP having an upper and a lower major surface and a set of CSP contacts along the lower major surface;
• a second CSP having first and second lateral edges and upper and lower major surfaces and a set of CSP contacts along the lower major surface, the first and second lateral edges delineating an extent of the upper major surface of the second CSP and the first CSP being disposed above the second CSP;
• flex circuitry connecting the first and second CSPs;
• and
• a substantially rigid form standard having an extent greater than the extent of the upper major surface of the second CSP and disposed so as to extend between the first and second CSPs and beyond the extent of the upper major surface of the second CSP;
• a switch controlled by a control signal for connecting a DQ signal to a selected one of the first and second CSPs of the high-density circuit module;
• a decode logic for generating the control signal that causes the switch to connect the DQ signal to the selected one of the first and second CSPs in response to a combination signal comprised of a clock signal and a chip select signal.

A memory access system comprising:

• plural memory expansion boards each populated with plural high-density circuit modules, each of which plural high-density circuit modules comprise:
• a first CSP having an upper and a lower major surface and a set of CSP contacts along the lower major surface;
• a second CSP having first and second lateral edges and upper and lower major surfaces and a set of CSP contacts along the lower major surface, the first and second lateral edges delineating an extent of the upper major surface of the second CSP and the first CSP being disposed above the second CSP;
• flex circuitry connecting the first and second CSPs;
• and
• a substantially rigid form standard having an extent greater than the extent of the upper major surface of the second CSP and disposed so as to extend between the first and second CSPs and beyond the extent of the upper major surface of the second CSP;
• plural multiplexers mounted upon each of the plural memory expansion boards, each one of the plural multiplexers corresponding to a selected one of the plural high-density circuit modules, each one of the plural multiplexers for making connections between a DQ signal and a selected single one of the CSPs comprising the high-density circuit module to which the selected one of the plural multiplexers corresponds;
• decode logic on each of the plural memory expansion boards, the decode logic for generating a control signal in response to a combination signal comprised of a clock signal and a chip select signal, the control signal causing at least one of the plural multiplexers to connect the DQ signal to a particular one of the CSPs.

A memory access system comprising:

• a memory board mounted with a high-density circuit module comprised of first, second, third, and fourth stacked individual CSPs;
• a switching multiplexer mounted on the memory board, which switching multiplexer provides selective individual connection of a DQ signal to a selected one of the first, second, third, and fourth stacked individual CSPs so that only one of the first, second, third or fourth stacked individual CSPs is connected to the DQ signal at a time;
• and
• a decode logic circuit for decoding chip selection signals from a control circuit and providing a switching multiplexer control signal.