On-chip test circuit for assessing chip integrity

A semiconductor chip having test circuit for assessing chip integrity, comprising:

• an active inner circuit;
• a die seal ring surrounding the active inner circuit;
• a first circuit structure fabricated at a corner of the semiconductor chip outside the die seal ring, wherein the first circuit structure has a first solder pad and is not electrically connected to the die seal;
• and
• a second circuit structure fabricated adjacent to the first circuit structure at the corner of the semiconductor chip and electrically connected to the first circuit structure, wherein the second circuit structure has a second solder pad;
• wherein neither the first circuit structure nor the second circuit structure is a part of the die seal ring;
• wherein by probing the first and second solder pads on the first and the second circuit structure simultaneously, interface delamination or chip cracking can be readily detected;
• once the interface delamination or chip cracking occurs, an electric loop, which was supposed to be a closed loop, is open, and therefore no current is measured.