Ultra-shallow metal oxide surface channel MOS transistor

A method for fabricating an ultra-shallow surface channel MOS transistor, the method comprising:

• forming CMOS source and drain regions, and an intervening well region with a surface;
• depositing a metal oxide surface channel on the surface overlying the well region having a thickness in the range in the range of 10 to 20 nanometers (nm);
• forming a high-k dielectric overlying the surface channel;
• and,
• forming a gate electrode overlying the high-k dielectric.

A method for fabricating an ultra-shallow surface channel MOS transistor, the method comprising:

• forming CMOS source and drain regions, and an intervening well region with a surface;
• depositing a metal oxide surface channel on the surface overlying the well region having a resistivity in the range between 0.1 and 1000 ohm-cm;
• forming a high-k dielectric overlying the surface channel;
• and,
• forming a gate electrode overlying the high-k dielectric.

An ultra-shallow surface channel MOS transistor, the transistor comprising:

• a source region;
• a drain region;
• a well region intervening between the source and drain with a surface;
• a surface channel overlying the well region;
• a high-k dielectric insulator overlying the surface channel;
• a placeholder overlying the surface channel, forming a temporary gate region;
• and,
• a gate electrode overlying the high-k dielectric layer, formed in the gate region.

An ultra-shallow surface channel MOS transistor, the transistor comprising:

• a source region;
• a drain region;
• a well region intervening between the source and drain with a surface;
• a metal oxide surface channel overlying the well region having a thickness in the range in the range of 10 to 20 nanometers (nm);
• a high-k dielectric insulator overlying the surface channel;
• and
• a gate electrode overlying the high-k dielectric layer.

An ultra-shallow surface channel MOS transistor, the transistor comprising:

• a source region;
• a drain region;
• a well region intervening between the source and drain with a surface;
• a metal oxide surface channel overlying the well region having a resistivity in the range between 0.1 and 1000 ohm-cm;
• a high-k dielectric insulator overlying the surface channel;
• and
• a gate electrode overlying the high-k dielectric layer.