US 7,256,462 B2Granted

Semiconductor device

AssigneeNEC Electronics Corporation

InventorSadaaki Masuoka

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Abstract

The present invention is to provide a high-quality semiconductor device allowing independent control of threshold voltage values of gate electrodes of transistors which reside in a plurality of one-conductivity-type regions and in a reverse-conductivity-type region. The semiconductor comprises a P-type Si substrate 109, a plurality of P-type wells 103a, 103b connected to each other via the bottom surface side of the P-type Si substrate 109, and an N-type well 101 provided so as to surround side portions of the plurality of P-type wells 103a, 103b. The semiconductor device also has NMOS transistors 107a, 107b provided on the P-type wells 103a, 103b, and PMOS transistors 105a, 105b, 105c provided on the N-type well 101. The semiconductor device still also has an N-type well 133 provided just under the N-type well 101 and connected therewith.

Claims9

Dependent claims

A semiconductor device comprising:

an one-conductivity-type semiconductor substrate;
a plurality of one-conductivity-type first regions provided at the element formation surface side of said semiconductor substrate, said plurality of first regions electrically connected with each other via the bottom side of said semiconductor substrate;
a reverse-conductivity-type second region seamlessly provided at the element formation surface side of said semiconductor substrate so as to surround the side portions of each of said plurality of first regions;
a first transistor provided on each of not less than two said first regions, and
a second transistor provided on said second region;
wherein the bottom portion of said second region in said semiconductor substrate is provided at a level of depth, under said element formation surface as a reference level, deeper than the bottom portion of each of said first regions in said semiconductor substrate.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/219,783Filed 7 Sep 2005
Priority: JP 2004-27453722 Sep 2004
Published: US 2006/0060923 A123 Mar 2006
Granted: 14 Aug 2007
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10W 10/30
Isolation regions in semiconductor bodies between components of integrated devices: isolation regions comprising PN junctions
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 84/0188
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their isolation regions
H10D 84/0191
The components including complementary IGFETs, e.g. CMOS devices: manufacturing their doped wells