Floating body-type DRAM cell with increased capacitance

A semiconductor memory device with floating body cells comprising:

• a plurality of transistors to constitute said floating body cells each having
• a semiconductor substrate,
• a first-conductivity-type semiconductor layer formed on said semiconductor substrate via a first insulating film, and having a single-crystalline structure,
• a second-conductivity-type source region and a second-conductivity-type drain region formed in said semiconductor layer,
• a first-conductivity-type body region formed between said source region and said drain region in said semiconductor layer, and said body region being electrically floating, and
• a gate electrode formed on a surface of a central portion of said body region via a second insulating film;
• an element isolation insulating film which isolates said body regions in adjacent transistors of said plurality of transistors;
• a word line which connects said gate electrodes of said plurality of transistors together;
• a bit line electrically connected to said drain region;
• and
• a source line electrically connected to said source region,
• wherein in a section along said word line, a length of a boundary between the central portion of said body region said second insulating film is smaller than a length of a boundary between said body region and said first insulating film;
• wherein a net impurity concentration in a surface portion of the central portion of the body region on which said second insulating film is formed is lower than a net impurity concentration in a region except for the surface portion.

A semiconductor memory device with floating body cells comprising:

• a plurality of transistors to constitute said floating body cells each having
• a semiconductor substrate,
• a first-conductivity-type semiconductor layer formed on said semiconductor substrate via a first insulating film, and having a single-crystalline structure,
• a second-conductivity-type source region and a second-conductivity-type drain region formed in said semiconductor layer,
• a first-conductivity-type body region formed between said source region and said drain region in said semiconductor layer, and said body region being electrically floating, and
• a gate electrode formed on a surface of a central portion of said body region via a second insulating film;
• an element isolation insulating film which isolates said body regions in adjacent transistors of said plurality of transistors;
• a word line which connects said gate electrodes of said plurality of transistors together;
• a bit line electrically connected to said drain region;
• and
• a source line electrically connected to said source region,
• wherein in a section along said word line, a length of a boundary between the central portion of said body region said second insulating film is smaller than a length of a boundary between said body region and said first insulating film;
• wherein the central portion of the body region on which said second insulating film is formed is completely depleted because a thickness of the central portion is smaller than a width of a maximum depletion layer formed when a predetermined potential is applied to said gate electrode.